Hi,
I am getting lotssof “Clearance violation (netclass ‘Default’ clearance 0.2000 mm; actual 0.0992 mm)” for via-in-pads, but not all of them as in the screen capture below
The via inherits the copper of the pad, hence the violation.
Either change the clearance or ignore the violation.
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Presume the clearance between GND pad and 3V3 via is < 0.1 mm, so the violation report is correct, not specifically related to via in pad.
The clearance is 0.2 mm
Pad to via clearance is < 0.1 mm according to your ruler (marked by the red line in my previous post). Not sure which clearance violation is reported to you, but I presume < 0.1 mm can’t be manufactured.
If pad hole is bigger than via hole then pad hole should be used for plating.
This is if pad x,y. matches via x,y.
Not hard to do clearance check in pcb entry in software.
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