Hey fellow sufferers ![]()
Any of you encountered these bugs using the via filler plugin? (Using KiCad 9.0.6)
It’s generating vias violating the edge cuts layer and also vias are placed inside the regular clearance close to copper traces.
Also using the plugin dialogue, I have to reenter all settings again if I’m not happy with the stitching result.
Can I trick the plugin to remember the last used settings and also integrate the list of predefined via sizes for the current PCB?
Cheers!
Hannes

