Via drill edge to adjacent trace clearance

[new_user_33]

I submitted my gerber to a fab house. Fab house requested a clearance of 0.3 mm between DRILL HOLE EDGE and ADJACENT TRACES (due to complications of copper thickness and fab process).

See below for example, My drill edge to adjacent trace is around 0.25mm.

I found this specific example manually. But I have hundreds of close gaps. How can I use KiCAD to help me

• Identify all the near gaps that are less than 0.3mm
• Auto adjust them (if KiCAD can’t do it, I’ll bite the bullet and do it manually)

In “Board Setup”, I didn’t find a place to specifically set/check the clearance between drill edges and traces. See below:

Side note, fab house allows 0.2mm clearance between traces. Therefore, increasing the clearance between traces isn’t an option for me, because I prefer to keep a tighter clearance between traces.

Thank you all.

[paulvdh]

It is a weird requirement.
This 0.3mm clearance implies some tolerance in the placement of the drill for the via, which is of course perfectly normal, but the drill should stay within the annular ring of the via itself.

And that is the closest solution that I know of that KiCad can provide.

For the “Default” Net class, you have a drill of 0.3048mm (Radius: 0.1524), and your manufacturer requires a 0. clearance.
Therefore, set the “Via Size” to at least 2*( 0.1524 + 0.3 - 0.2) = 0.5048mm
This keeps the 0.2mm clearance in your design rules, while it forces other tracks to keep further away from the via’s.

These bigger via’s also allow for the placement tolerance of the drill. Note that in a normal PCB process, the via holes are drilled and plated before the PCB is etched. Alignment between the various process steps is normally done by some reference holes in the big panel.

[new_user_33]

Thank you. This is what I was thinking too.

My challenge with this method is: I can set the “Via size” in the net class, but I don’t know how to apply this new via size (0.5048mm) to all the associated vias in this net class. If that’s doable, then bingo.

Another solution I can think of is to: Change the via footprint pad clearance to 0.3mm. Similar to this post:

Way to set copper pad clearance different than track clearance?

Is there a way to set pad clearance (for copper) different than track clearance (for copper)? Under the Design Rules Editor, Net Classes Tab there is a Clearance field. In the Global Design Rules tab there is table for custom via sizes but it only has pad size and drill size. No field for pad clearance. Under the Dimensions pulldown there is a tab for Local Clearance and Setting but this appears to be for mask and past clearances. I want to set the copper clearances differently for pads than f…

However, I can’t find the footprint for via … am i dumb?

[paulvdh]

In your case, you first set Pcbnew / File / Board Setup / Design Rules / Net classes (Which is the screen you made a screenshot of) and increase the rules for your via sizes.

Next step is:
Pcbnew / Edit / Edit Track & Via Properties

Then you can use the filters, and actions to modify the via’s.

This does not modify the location of the via’s, or of adjacent tracks, so setting the via size to a bigger value will lead to a lot of DRC violations, which you have to solve afterwards.

Setting up de design rules for your PCB manufacturer should be one of the first steps when the schematic is finished and the PCB work is started.

[new_user_33]

Thank you a lot! That answered my question and I’ll deal with the numerous DRC violations afterwards.

I do understand that I missed this step before PCB work. You made my day!

[Naib]

@paulvdh

It is a weird requirement.
This 0.3mm clearance implies some tolerance in the placement of the drill for the via, which is of course perfectly normal, but the drill should stay within the annular ring of the via itself.

While it does sound weird (as it implies a hit accuracy) it is how some places state their capability.
https://jlcpcb.com/capabilities/Capabilities

I think it is more of an over-specifying than a specific constraint as the key here will be annular ring size (implies their hit accuracy) and copper-copper (etching capability)
I suspect they and others have been asked “what about this, what about that” or … “but you didn’t say you couldn’t do this” and as a result over-specifying is the simplest answer