On one of my boards I had a via connected to both the 5V and ground plane. I thought this would not happen because the DRC would check for that. In the future how can I avoid this mistake ? I ended up have to drill out the via and put wire mods on my board to fix this issue.
Well we might need a bit more detail.
First of all what kicad version. What canvas?
Did you run DRC before creating your gerbers? (What is the exact DRC output if you run it on the original files? Does DRC list unconnected nets?)
Are filled zones involved?
Could you show a screenshot of the affected area?
How did you add the via?
(Is it possible that it is a blind/burried via or even a micro via? Or maybe it is a manual stitching via with some wrong settings.)
Is it possible that the two nets are connected in the schematic?
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Given a suitably beefy power supply, it won’t stay connected for too long.
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Any chance of putting up the pcb file for us to have a look at it?
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If a rogue via connects GND to Vcc I understand drilling it out as a solution. But why:
Why were the wire mods nessasarry?
How many errors were there in total on this PCB?
How much experience do you have with KiCad in general?
Is it a simple beginner project, or a complex PCB (Such as the Olimex boards)?
If KiCad does not catch such an error with DRC it would be a pretty serious bug.
On the other hand, a lot of easy mistakes can be made, such as:
- Forget to update the netlist from EEschem -> PCBnew.
- Forget to run DRC on the last design iteration.
- Forget to make new gerbers after the PCB is modified.
- Error in a Fooprint (one of the many GND connections of a IC is accidentally connected to Vcc).
- Send Old version of the gerbers to a PCB fabhouse.
Can you check if any of the above (or other) errors were made?
Like davidsrsb, I’m curious to see the project files posted here (Including the Gerbers?).
Are you willing to publish it?
Battery_Charger_rev02.kicad_pcb (790.4 KB)
I have attached the PCB file. It seems like I created my gerber files before running one last iteration of DRC check. When I run DRC check these issues are fixed.
An example of where the VIAs overlapped is on U1 the via going to 5V.
I have uploaded it in one of my replies below.
DRC usually has refill all zones ticked. (very important)
KiCad plot does not automatically refill, (or even warn, when fill info is obsolete) and when I suggested that was less than ideal, and prone to user errors, the developers imagined it was a feature.
Even a separate button called [refill and plot] would be smarter, or a plot with DRC as default, forcing a user to have to try really hard to avoid DRC and (correct) refill…
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If it is any consolation, I did a moderately complicated schematic in KiCad, but didn’t have the time to do the layout. I farmed it out to a board house who hired a layout guy with 30+ years of experience. The boards ($10K total) came back with 20 errors, Half of which were vias with connections to both the power plane and GND. +12V, +5V and +3.3V all connected to ground. The other errors were signals connected to power or ground. They built new ones but it was an awfully expensive mistake for me in terms of time and effort and for them having to redo the boards. Never got an explanation for how it happened.
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