Via clearance too large?

Layout
1

Hey folks, I’m trying to layout a 6.5mm pitch BGA chip, and I’m seeing what I believe is odd behavior regarding via clearance.

When I start drawing a trace, and then press ‘v’ to add a via, the clearance appears to be much larger than the configured net class.

Then after I click to create the via, the clearance appears to shrink to what appears to be the appropriate configured size.

I’ve compiled some screenshots into this image to illustrate what I’m seeing. Please forgive me for creating a single image; I’m a new user so I’m limited to one image per post.

via-clearance
via-clearance1487×2306 270 KB

I cannot move the via after it is created (it appears to use the larger clearance?).

Is there a setting I’m missing?I believe this should result in a ~0.356mm via with ~0.096mm of clearance, or a total diameter of ~0.548mm, which should fit in the diagonal center of 4 BGA pads at 0.65mm pitch. But I’m unable to put the via in that verical center.

Forgive me if I’m missing something silly, this is my first time working on a BGA layout.

2

That seems a bit biggish, but I can’t tell from a screenshot :slight_smile:

The clearance of your via’s does seem to be changing. The clearance around the three via’s on the top of your screenshot are even bigger. (Did you regenerate zone geometry by hitting the b key recently?)

Do you have complicated things in your setup such as custom rules or rule area’s?

Maybe it is some sort of bug. If so, it helps if you upload a simplified version of your project (make a copy, delete most of the schematic and PCB, but leave the BGA with some tracks and vias and something to connect those nets to for the netlist).

For analyzing bugs, also always include the full version information from: Help / About KiCad / Copy Version Info and then copy it in a post here.

3

Okay, here is a zip that contains the project with everything but the BGA chip removed: https://snds.gd/bga-via-issue-52519.zip (unable to add here because I am a new user).

I was able to reproduce the same behavior described in my previous post without any additional components. Just open in pcbnew, draw a trace from any BGA pad, and try to drop a via in the diagonal center of 4 pads.

Did you regenerate zone geometry by hitting the b key recently?

I usually hit b after I make an edit. This is on a four layer board, and every layer has a ground plane with 0.254mm clearance.

Do you have complicated things in your setup such as custom rules or rule area’s?

No.

version info from project window:

Application: KiCad x86_64 on x86_64

Version: 8.0.3+1, release build

Libraries:
	wxWidgets 3.2.2
	FreeType 2.12.1
	HarfBuzz 6.0.0
	FontConfig 2.14.1
	libcurl/7.88.1 OpenSSL/3.0.13 zlib/1.2.13 brotli/1.0.9 zstd/1.5.4 libidn2/2.3.3 libpsl/0.21.2 (+libidn2/2.3.3) libssh2/1.10.0 nghttp2/1.52.0 librtmp/2.3 OpenLDAP/2.5.13

Platform: Debian GNU/Linux 12 (bookworm), 64 bit, Little endian, wxGTK, X11, , tty
OpenGL: NVIDIA Corporation, NVIDIA GeForce RTX 4090/PCIe/SSE2, 4.6.0 NVIDIA 535.183.01

Build Info:
	Date: Jun 11 2024 18:33:50
	wxWidgets: 3.2.2 (wchar_t,wx containers) GTK+ 3.24
	Boost: 1.74.0
	OCC: 7.6.3
	Curl: 7.88.1
	ngspice: 39
	Compiler: GCC 12.2.0 with C++ ABI 1017

Build settings:

version info from pcbnew:

Application: KiCad PCB Editor x86_64 on x86_64

Version: 8.0.3+1, release build

Libraries:
	wxWidgets 3.2.2
	FreeType 2.12.1
	HarfBuzz 6.0.0
	FontConfig 2.14.1
	libcurl/7.88.1 OpenSSL/3.0.13 zlib/1.2.13 brotli/1.0.9 zstd/1.5.4 libidn2/2.3.3 libpsl/0.21.2 (+libidn2/2.3.3) libssh2/1.10.0 nghttp2/1.52.0 librtmp/2.3 OpenLDAP/2.5.13

Platform: Debian GNU/Linux 12 (bookworm), 64 bit, Little endian, wxGTK, X11, , tty
OpenGL: NVIDIA Corporation, NVIDIA GeForce RTX 4090/PCIe/SSE2, 4.6.0 NVIDIA 535.183.01

Build Info:
	Date: Jun 11 2024 18:33:50
	wxWidgets: 3.2.2 (wchar_t,wx containers) GTK+ 3.24
	Boost: 1.74.0
	OCC: 7.6.3
	Curl: 7.88.1
	ngspice: 39
	Compiler: GCC 12.2.0 with C++ ABI 1017

Build settings:
4

It is some kind of interference with: PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to hole clearance. If I set this to a smaller value, then the extra clearance is gone.

It is sort of logical I guess. If you specify a clearance between a hole and copper (from another net), then KiCad takes the biggest of the two clearances, and if you have very small vias then this copper to hole clearance is bigger then the via annular ring plus the track clearance. At least, I think that is what is happening here.

1 Like
5

Reducing PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to hole clearance to 0.127mm makes the issue go away for me :smiley:

Thank you! I was manually moving the vias, but I have a feeling this will cut back a ton of the noise when I run the DRC.

1 Like
6

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.