I wish to set the via outside to copper clearance of 0.127mm. I set in pcb setup the copper to hole constraint to 0.127mm and then change the clearance in the layer to 0.127mm. For some reason the clearance cannot be less than 0.15mm no matter the constraint. No via’s, traces or anything else is near the via’s . Kickad 6. what else influences this other than those to settings ?
The zone itself has a clearance setting, check that it is set to 0.127mm or smaller.
I set “electrical properties” => clearance to 0.127mm, it has no effect, the clearance stays 0.15mm,
Use the Inspect > Clearance Resolution tool between the zone and the via (select both of them and then run this tool, then see what it says)
I assumed that setting was for nets and not for copper zones. Not fixed. Still checking…
Yup, copper zones are part of a net too. A net just means all connected copper (not just tracks and pads)
The clearance jumped to 0.2mm now after setting it to 0.127mm,. I have all set to 0.127mm but the clearance is now 0.2mm.
EDIT: OK, now, I checked the wrong NET with different settings. OK now. ! Thanks !
The only things is , I want to have a different clearance for the via in the ground plane (copper zone) than for the same NET and via in the signal layers… Setting a net CLASS for GND signal only did not work
The case is is that the clearance in the inner layer 0.127mm is fine, but the traces and vias on signal layers need to stay 0.2mm
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