Very Close Trails


#1

Hello, I have a problem with the layout of the board I’m making, it says the following error “Tracks very close to the track” and I can not solve it. Can someone help me please?! I’m using google translator.


#2

Go to the “Design Rules” drop-down in the top menu bar. Verify that you have reasonable values for “Clearance” in each of your Net Classes.

Dale


#3

Your track width is too high for the SOIC pad width and spacing


#4

I don’t know if the widths or clearances are an issue but it looks to me like he/she is laying out a double sided board with SMD components but no vias. There are both red and green tracks that look like they are attempting to connect to SMD pads, and some that overlap but there doesn’t appear to be a via connecting them.


#5

We might as well explain that vias are placed by using the v key while in track mode.

(Vias are plated through holes intended to connect copper features on different layers.)


#6

I took a close look trying to guess the native tongue and this looks to be a 2013 version of KiCad? Are some versions just out of date because no one keeps the translations updated?


#7

I see that now. Maiza should definitely upgrade to the current release 4.0.7, but that does not appear to be the problem causing the error message.

I am not convinced of this. On my display, it looks like the track width at U2 is slightly less than the pad width.

I suggested the Design Rule “Clearance” problem because I can not determine what is happening at C3 - too many colors and features are smeared together.

Dale


#8

At C3, the track coming from the middle pad of U1 is touching, or too close to, the GND pad.

For the other raised questions, it is 2013 version, language is Portuguese, no vias at all.
The version reference is never translated.

@Maiza_Vitoria: if you are using google translator, maybe you want to ask your question to http://www.elektroquark.com/forokicad/index.php in Spanish.


#9

Hi,

From what I see is that you have a Problem from the Center pin of U1 to the C3

saludos Rainer


#10

Aside from the lack of vias and the obvious layout error at C3 this could easily be a single sided layout with improved component placement. And the footprint pinout for the 7805 is incorrect.


#11

Hermit has sharp eyes.
I can zoom in on OP’s KiCad screenshot:
2018-04-08T04-24-49_KiCad_2013