Verify gerbers with netlist


I wonder if there is a tool or way to verify gerbers with the netlist file. When I generate my gerbers I am pretty confident that they are correct, as I run DRC, ERC ,etc. However sometimes due to lack of time I would externalize the panelization to a pcb supplier and in the last order boards came with a short. So is there a way to verify that the panel gerber is correct using the netlist file ?


Allpcb do a flying probe board check at no additional cost.

Allpcb. They need a netlist before they can do an electrical test. Which netlist do they use?

JLCPCB needs no netlist for their free flying probe check. They compare the Gerbers to the board, based on the copper. I think all the low cost manufacturers do the check that way.

Do you use netlist files in your normal workflow?
This has been deprecated for years. These days Schematic Editor / Tools / Update PCB from Schematic [f8] is recommended.

DRC if pretty thorough, and this makes me wonder what the underlying error was that caused a short on the PCB. I once had a matrix board with 6 shorted pads due to a hair on it during the creation of the mask layer for etching.

If you send your PCB’s off for panelization, they are not going to create shorts somewhere in the middle of your PCB. At the moment I’m guessing that the short was in the design, and then it would also have been in the netlist, and this extra check would not have caught it. Maybe you made a little change and forgot to run DRC as a last step before making Gerbers?

I recommend to use a checklist to go through before creating gerbers, and whenever you find an error, fix it, and then restart with the checklist.

It’s called AOI (Automatic optical inspection). I recently saw a factory walkthrough of one of the big Chinese PCB manufacturers. They hover a camera over the PCB just after etching (so before silkscreen is applied) and they compare the pictures with the gerber files. If done properly, this could be better then mechanical flying probe tests that actually take measurements. For example an etch fault that leads to a small very narrow (but not interrupted) section on the PCB can be detected this way.

You are right. Obviously no flying probe involved.

That goes for AOI. They do an electrical flying probe check as well, again without netlists.

Exactly. Therefore it the error is in the Gerbers, the electrical test will not find it, using this worklow.
However, if you send the true netlist, you can find errors in the Gerbers.

No, the mistake was not in my design, I double-triple check that before sending anything. Manufacturer connected a via to a track by mistake when panelizing. why? I don’t know. As you can expect, when they sent me the panel gerbers for review I didn’t check all the connections in all the layers but verify that the panel had a correct distribution and outline. They’ve already remade the panel free of charge because of this. However I was wondering what extra check or extra file I can provide to avoid that in the future. Next time I’ll do the panel myself but for this spin I didn’t have time for it.

That’s what I want to know. If netlist is provided, can you catch these problems? From pcbnew I see that there is a IPC-D netlist option under fabrication output, together with genCAD that should be it I suppose ?

KiCad can embed netlist info directly into the gerber file:

You can also verify this in KiCad’s gerber viewer. It has drop down boxes to select a net, and then that net is highlighted.

If you provide a netlist with your design, most fabricators will check whether it matches the image. IPC is a fine format for transferring the netlist, however I do not know how good the KiCad netlist is.
As paulvdh writes, you can also include the netlist in the gerbers, and these are good.

As an alternative, you can also do a graphical comparision between your own gerber files and the gerbers for the whole panel. Ideally you would overlay them with an XOR function. This brings up any difference immediately. This is however not supported by KiCad directly as far as I know.

I think this works:

  1. Load a (set of) Gerber file(s) into KiCad’s Gerber Viewer.
  2. Gerber Viewer / File / Export to PCB Editor
  3. PCB Editor / File / Plot / Plot format: … (Use whatever fits in the next step).
  4. Open the files in some suitable graphical drawing program.

Maybe you can also use programs such as KiCad-diff, but I have no experience with them.

That’s worth checking out, thanks a lot

I see. I might have missed ticking ‘Including netlist attributes’ box when exporting or the netlist attributes got ‘lost’ when panelizing? (speculation here). Thanks I’ve just verified that I can check in kicad gerber viewer the netlist info and highlight it.

Generally speaking providing a netlist (IPC-D-356A) together with Gerber and Excellon files for bare board fabrication is a very good idea. Yes, the manufacturer can regenerate a netlist in their CAM tool from the artwork but that’s only half-good.

I always add the following statement to board fabrication notes: “Full netlist electrical verification for opens and shorts shall be performed on all bare boards using customer supplied netlist”

It will be even better when KiCad supports outputting manufacturing data in ODB++ and/or IPC-2581 formats as they allow embedding netlist into them.

So do gerber files these days (And it’s already supported by KiCad, as mentioned earlier in this thread.
I never looked much into DB++ and/or IPC-2581 formats, but from what I gather they’re pretty much equivalent to modern Gerber, with each camp claiming their own standard is the best.

1 Like

Well, as I understand, Gerber X2 format supports netlist data but not many board fabricators support Gerber X2 yet :slight_smile:

Allpcb do do flying probe. I see the probe marks on the pads.