I was surprised that KiCad release V6 would have this issue.
In my opinion, the label should terminate the wire, and if is not the case then ERC should flag an error.
If, for schematic presentation, then a graphic line item should be made easily available to visually extend the connection for printability.
Are you sure that’s a net label? It looks like a text label to me. A net label would make the square disappear and appear much closer to the end of the pin. Also whether a no-connect error is raised depends on the type of the MISO pin. Many symbols imported from outside KiCad set pins to Undefined or Passive.
How many more screen-grabs do you want me to provide?
Your can check it yourself, just select the pin and the net it’s connected to will be shown in the status area. Also every pin I’ve attached a net label to no longer has a square end. So either it’s not a net label or you haven’t attached it to the pin.
The square end is still here on my end. I don’t like them though, so I almost always trim my stubs so they terminate at the label.
This is probably not an ERC violation because that net (MISO) is in fact connected to something. What you are talking about here is a visual User Interface thing, and while you don’t like it it very well may be that others do.
Say you have a bunch of nets, with different length label names. Maybe you want all the green lines to be equally long? Maybe it should should point to a line drawing or image.
Simly shorten the wire if it bothers you 
However, if MISO is not connected to anything then you’ve found a bug and should post your project here (for us to double check, feel free to narrow it down and hide any secret sauce) and maybe file an issue with the gitlab repository.
And what is exactly your issue?
Do you not like the square at the wire end?
Were you expecting some message in the Violations tab page?
Maybe something else?
I just refuse to guess about things like this, because it leaves too much room for misinterpretations.
This is not a bug.
A label attaches to a wire anywhere along the wire, it is not necessary to place it at the end of the wire. If a label is placed in the middle of a wire, the dangling end (square box) will still show up on the end of the wire that has no pin or junction (as you show in your screenshot) but this is not a problem.
Having a dangling end (the square box) on a wire is not an ERC issue by itself. The net may be connected to other pins by labels (not directly).
Maybe it should be considered as being a Bug?
I’ve not used KiCad in a couple of months; and was using V5 when I did. This project was created with V6 and required me to download V6 to open it. From the perspective of a fresh set of eyeballs on a new schematic, this looks to me like something is not working properly.
Obviously it is an opinion that I hold, and perhaps the devs don’t care what my opinion is.
But, to further the discussion, I guess it depends somewhat on the scope of the situation. The project was created by an individual more familiar with Altium. Me, a only used Altium for 10 minutes user, and more familiar with KiCad was not able to determine the intent of the schematic with it having “no-connects” at the end of the wire lines.
I had to contact, by phone call, the invidual that created the schematic to understand what his intent was with the unconnected ends of the wire lines. This seems like some issue is a “bug” to me; although maybe it is considered a KiCad feature at this point in time.
It is my opinion that if something is indicated as “no-connect” then the default ERC should flag that issue.
Wether or not a wire line with a label anywhere along the line should have the end show a “no-connect” is a seperate issue. In this case it would be my opinion that there is not a good current solution in KiCad.
the little green square is not a “no connect”-sign.
No connect is indicated with a diagonal cross.
Well, NOW I SEE where the confusion is from.
If you have read this far, it is my opinion that the “dangling end”, with the square box, should by default flag an ERC error.
Everyone now happy?
No, I am not because the last picture does not reflect the same situation as shown in the initial diagram. In the first diagram the net seems to have been labeled, called MISO. In the latter, there’s not even proper annotation been done, recognizable by the question mark after the variable resistor RV. The original post is not an ERC in my opinion. It’s just a dangling piece of wire in the schematic.
Uh, I think mf_ibfeew just made a quick diagram to show the difference between a dangling end and a no-connect symbol, it doesn’t matter that the symbol in that diagram isn’t annotated…
Not quite.
I do see your point though.
Part of it was probably as mf_ibfeew (is that his/her real name?) showed the difference between an open square and a “no connect” flag.
The “open end squares” in themselves are harmless, although I do find them ugly. Often I hide them by mirroring a label and placing the attachment point of the label on the end of the wire.
Although open wire end squares are completely benign, they may be an indication of “something still todo”. From that point of view I can say that adding them to the ERC could be useful. But because they are harmless on themselves I do recommend to set them to “ignore” by default.
Is this an idea that would be useful enough to implement? Or is it just a bit of silliness?
Then forget about the dangling end. It’s dangling in both cases, except that the original post shows net name MISO. If there’s a label somewhere else to another wire, it’s effectively connected, isn’t it?
This would add a ton of noise to ERC for not any real benefit. ERC is supposed to warn you about real problems with your schematic that may result in the circuit not working or not being connected the way you think… Just the presence of a dangling-end indicator does not indicate that the wire is not connected anywhere else in the schematic.
Dangling End is a KiCad-specific term that refers to the green square at the end of the wire. I am using that term here specifically, I am not talking about a “generic dangling end”. So no, in the screenshot, one wire has a Dangling End and the other has a No-Connect Symbol.
In this case, there is no difference between these two except for what they look like. The ERC will determine whether or not to warn about the wire based on whether or not it’s actually connected anywhere else (maybe via a label). The ERC does not care whether you place a no-connect symbol on the end of a wire (to get rid of the Dangling End symbol), or whether you flip around the label so its connection point lies at the end of the wire (as suggested by Paul).
I do not remember them to be completely benign; but I’ve been using KiCad since early V3.
It is my current opinion that passing ERC on “dangling-end” wire lines is bad practice.
How do I KNOW that DRC on the final board design is correct? ERC and DRC should provide a 100% error free design. How does ERC not flag a dangling wire line?
Last thought; add in the same feature in PcbNew to Eeschema to “remove” dangling wire lines.
How would an average/new user know that?
On Edit: I did not even know that.
What’s wrong with it? It’s benign as long as it will be reported by ERC if the wire is part of a net that has either no port or just one port.
Yes, I understand that, and that Is why I suggest to set them to Ignore by default.
But because I already have a tendency to clean up such dangling ends by for example mirroring labels, appearance of dangling ends may indicate some accidentally deleted wires or a moved object.
I think I would actually like these things to be flagged near the end of a design cycle. To me they are an indication of KiCad telling me: “Hey, I see somthing and I don’t know what it means, will you have a look at it”.
With the latest improvements in the ERC system it’s quite easy to leave it at “ignore” if you don’t like the feature. And if you turn it on because you think it’s useful you can also flag individual open ends as being ok.
Paper schematics in the field suck; keep that in mind.
