It’s always been like that. It’s been noted before that you can’t set a default value in the footprint, the text is just a placeholder that gets overwritten.
You might want to change the title. It also confirms my THEORY about people who put RANDOM words in caps… Rather than leaping to conclusions, why not ask first?
No, it has not.
I used this quirk to create a seperate drawing with only the Fab Layer.
C5 was fully qualified for what I wanted on all the layers; including the NON-Fab layers. I was able to select the layers of interest and create and print a document that illustrated the properties of the parts on the board.
I suppose I should probably move all of the Fab layers in my library into one of the other layers; that is going to be quite a bit of a time sink.
Bottom line, I WAS using KiCad to create secondary documents by printing those layers. I’m now going to have to wait to see what happens with release of V5 before I spend to much time on my own personal libraries.
It has nothing to do with what layer the value field is on. It is always handled the same way.
Can you explain which steps work, or used to work.
If there is a value in the SCH, that would be expected to export in the NET.
However I can see uses where someone might want to load some default LIB value, and in order to do that, omits value line from the NET. Other CAD pgms work like this. ie info not in net, comes from lib.
In that somewhat special case, I would expect NET import into PCB to load the LIB part, with LibVal
Strangely, in an (older) Version: (5.0.0-rc2-dev-44-gde6b32d23) I get this behaviour
I can create a custom LibValue field in LIB, and manual add-part, brings that in fine.
NET import, with no value line at all, (edited NET file) brings in an empty value part.
After that is imported, I can still manually add from lib, and LibVal shows on NEW manual footprint.
However, neither update from lib nor change footprint will get the LibVal updated on any existing part ?
To me that is a blind spot.
Smarter LIB/NET combined operation would be :
Currently, you appear to have a situation where a LIB change, cannot be applied to an existing design.
When I download a new nightly, I’ll recheck this. << Addit: Identical on latest build.
I can not quite remember all the details of the different versions I have used!
My biggest issue, from what I recall, is that if I wanted to make a VERY SMALL change to the footprint dimensions, then ALL of the silkscreen and Fab layer information was dorked up in location and rotation upon reading the new NetList.
Silly me thought it might be a good idea to seperate and include the two concepts. I’d have an Atomic Symbol that had an Atomic Footprint. It worked in KiCad for a while.
As a reminder, this issue has NOTHING to do with board fabrication, but is related to how I attempted to use KiCad to create an IPB with location and value not changing even if the Land Pattern of the Footprint was changed.
At the moment, it looks like I may retain the same concept, but move the Atomic Footprint data off of the Fab_Layer in KiCad.
My further thinking was that even if a part had the same Land Pattern, it might physically have a different height and benefit from other tweaks in design.
I’m not an expert in any way, but I already have 2 separate 1206 FootPrints for resistors and capacitors.
I figured that that even though the Land Pattern dimensions might be the same, the Solder Paste and Solder Mask might not be the same.
My very first attempt at Atomic FootPrints is apparently a failure.
As i explained above, you use the atomic idea wrong.
A proper atomic pair has a symbol specific to your footprint. The symbol holds all the data (reference, value, mpn, …) whereas the footprint is made in the normal way.
So if you then update from schematic you get the correct data from the atomic symbol into the placeholder fields of your footprint.
Mainly because the 3d model is different (resistor has a black body, capacitor a brown body)
But also because users will expect a resistor footprint for resistors and a capacitor footprint for capacitors.
In the case of resistor vs capacitor they are equal (both fall under the same IPC rules) In the official lib both footprints are generated by the same script.
The default libraries always did this as the end metalisation is very different, before you even start thinking about the different 3d models
What do you mean with “end metalisation”? The 1206 footprints in the resistor, capacitor, diode, … libs are identical with respect to the footprint data. (only the description, tag and 3d path are different. You can easily check that using a text diff tool.)
I am talking about the part, not the footprint
I am still not really clear why that would need different footprints. (which after all is what the discussion is about)
There was a time when V4 hand soldering footprints did vary
I was interested mainly in 0603. As resistor has less metalisation then capacitor you can put resistor on capacitor footprint. At least I don’t know of any problems comeing from it, but who knows. But why not have more room betwean resistor pads. KiCad R_0603 (4.0.7) had a gap of 1mm betwean pads (C_0603 had 0,7mm). In 1mm you can run two 0,2mm tracks.
The current version 5 footprints use fillet sizes as defined in IPC-7351B. We use the default placement and PCB manufacturing tolerances as listed in the same standard.
We use the component size definitions found in an old ipc document. (at least for the most common sizes.)
I checked them against a few components on farnell. Over all parts i checked (i think i checked 10 to 20 parts for 5 to 10 manufacturers depending on size) i got the same variation of component sizes as given in that old standard.
If you limit yourself to only one exact part you will most likely be able to get smaller tolerance ranges resulting in smaller pads and most likely larger pad to pad clearances. (So if you really need the space you will most likely make a unique footprint for the parts you plan on using.)
This is especially noticeable for 0805 as this has a smaller clearance than 0603. After 5 arbitrarily selected parts i was already quite close to the tolerance ranges used by us. Checking 10 further random parts even increased it on the toe side. (I found quite a few exactly matching the heel side) Nearly every single part could have had either a reduction on the heel or toe side. (Agrees with my suspicion that specialized footprints can help you out if you are pressed with space.)
The old kicad 4 footprints pads where too small for most parts i checked. (I could not find a single component that would have fit the old 0603 or 0805 footprints if you respect the tolerance ranges given in the datasheets. Even if you ignore manufacturing tolerances.)
I know one designer who created a whole series of CAP footprints, where the paste area, varied by the CAP thickness. Same nominal 0805, but significant variation in solder paste.
Something like that would require specifically more information about the manufacturing process used then we at the official lib have. (Is however a good tip for anybody creating their own libs.)
That is why the paste coverage is not specified for most footprints. Only exceptions are very small SMD two terminal footprints where we found a detailed paper giving advice on limiting the paste coverage on the heel side. And exposed pads also have special paste handling. And some specialized packages where the manufacturer gives a detailed suggestion for how paste should be handled
I have no knowledge about tolerances etc…
But when looking through 4.0.7 footprints I found:
Lets see where IPC-7351B would lead us:
lets call the distance between the leads on the inside S.
Smin = Lmin - 2*T1max = 0.5Smax(rms) = Smin + sqrt(Ltol^2+2*Ttol^2) ~ 1.085 (That is already quite close to 1mm and we are looking at the statistical maximum here!)with default manufacturing tolerances (0.1 placement § and 0.05 pcb manufacturing (F)) we get and 0 heel fillet (Jh).
l = Smax(rms) - 2*Jh - sqrt(Ltol^2 + 2*Ttol^2 + P^2 + F^2) ~ 0.5
because of rounding (to 0.05 as suggested by IPC), even without manufacturing tolerances we get the same result.
(By the way Ttol = Tmax - Tmin -> 0.4! and this tolerance comes into play twice. i would guess it is the largest contributing factor.)
IPC-7351 suggested -0.05 hell fillet and rounding to 0.2
l = 0.6
So i would take that suggested footprint with a grain of salt to be honest.
The calculation above uses the formulas for IPC-7351 but the fillet sizes for IPC-7351B (I did not notice that not only the fillet sizes have been changed but also the way how tolerances are respected.)
The change is in how Smax(rms) is calculated.
And using the already known calculation from above to arrive at the pad to pad clearance:
l = Smax(rms) - 2Jh - sqrt(Ltol^2 + 2Ttol^2 + P^2 + F^2) ~ 0.65 (rounded to nearest 0.05)
Notice we have a slightly larger pad to pad clearance but still nowhere near to what the datasheet suggests.
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