I was interested mainly in 0603. As resistor has less metalisation then capacitor you can put resistor on capacitor footprint. At least I don’t know of any problems comeing from it, but who knows. But why not have more room betwean resistor pads. KiCad R_0603 (4.0.7) had a gap of 1mm betwean pads (C_0603 had 0,7mm). In 1mm you can run two 0,2mm tracks.
The current version 5 footprints use fillet sizes as defined in IPC-7351B. We use the default placement and PCB manufacturing tolerances as listed in the same standard.
We use the component size definitions found in an old ipc document. (at least for the most common sizes.)
I checked them against a few components on farnell. Over all parts i checked (i think i checked 10 to 20 parts for 5 to 10 manufacturers depending on size) i got the same variation of component sizes as given in that old standard.
If you limit yourself to only one exact part you will most likely be able to get smaller tolerance ranges resulting in smaller pads and most likely larger pad to pad clearances. (So if you really need the space you will most likely make a unique footprint for the parts you plan on using.)
This is especially noticeable for 0805 as this has a smaller clearance than 0603. After 5 arbitrarily selected parts i was already quite close to the tolerance ranges used by us. Checking 10 further random parts even increased it on the toe side. (I found quite a few exactly matching the heel side) Nearly every single part could have had either a reduction on the heel or toe side. (Agrees with my suspicion that specialized footprints can help you out if you are pressed with space.)
The old kicad 4 footprints pads where too small for most parts i checked. (I could not find a single component that would have fit the old 0603 or 0805 footprints if you respect the tolerance ranges given in the datasheets. Even if you ignore manufacturing tolerances.)
I know one designer who created a whole series of CAP footprints, where the paste area, varied by the CAP thickness. Same nominal 0805, but significant variation in solder paste.
Something like that would require specifically more information about the manufacturing process used then we at the official lib have. (Is however a good tip for anybody creating their own libs.)
That is why the paste coverage is not specified for most footprints. Only exceptions are very small SMD two terminal footprints where we found a detailed paper giving advice on limiting the paste coverage on the heel side. And exposed pads also have special paste handling. And some specialized packages where the manufacturer gives a detailed suggestion for how paste should be handled
I have no knowledge about tolerances etc…
But when looking through 4.0.7 footprints I found:
and there (page 120 = page 3 of pdf) 0603 reflow soldering was the same as KiCad R_0603).
Lets see where IPC-7351B would lead us:
lets call the distance between the leads on the inside S.
Smin = Lmin - 2*T1max = 0.5
Smax(rms) = Smin + sqrt(Ltol^2+2*Ttol^2) ~ 1.085(That is already quite close to 1mm and we are looking at the statistical maximum here!)
with default manufacturing tolerances (0.1 placement § and 0.05 pcb manufacturing (F)) we get and 0 heel fillet (Jh).
l = Smax(rms) - 2*Jh - sqrt(Ltol^2 + 2*Ttol^2 + P^2 + F^2) ~ 0.5
because of rounding (to 0.05 as suggested by IPC), even without manufacturing tolerances we get the same result.
(By the way Ttol = Tmax - Tmin -> 0.4! and this tolerance comes into play twice. i would guess it is the largest contributing factor.)
IPC-7351 suggested -0.05 hell fillet and rounding to 0.2
l = 0.6
So i would take that suggested footprint with a grain of salt to be honest.
The calculation above uses the formulas for IPC-7351 but the fillet sizes for IPC-7351B (I did not notice that not only the fillet sizes have been changed but also the way how tolerances are respected.)
The change is in how Smax(rms) is calculated.
- Smax = Lmax-2*T1min = 1.45
- Smin = Lmin - 2*T1max = 0.5
- Stol = Smax - Smin = 0.95
- Stol(rms) = sqrt(Ltol^2+2*Ttol^2)~0.585
- Smax(rms) = Smax - (Stol - Stol(rms))/2~1.26
And using the already known calculation from above to arrive at the pad to pad clearance:
l = Smax(rms) - 2Jh - sqrt(Ltol^2 + 2Ttol^2 + P^2 + F^2) ~ 0.65 (rounded to nearest 0.05)
Notice we have a slightly larger pad to pad clearance but still nowhere near to what the datasheet suggests.
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