Hello, I’m trying to make a simple board which is basically composed by 2 identical rectangles. They are adjacent and they have a V-cut in the middle, it’s always been fabricated correctly.
Problem is: Kicad doesn’t recognize this as a closed shape, it always gives a DRC error (malformed shape or self-intersecting polygon, depending on how I create the shapes).
How do I define the board shape in order to avoid DRC errors? What’s the correct procedure?
Thanks in advance.
If your board manufacturer wants the V-cut on the Edge.Cuts layer you are going to have to live with the DRC error
Gerber (X2) files support a .FileFunction Vcutmap, and thus V-cuts should be in a separarate layer, but this is not supported (yet) by KiCad. (And I guess many other program’s don’t support it either)
Your way of putting the V-cuts on Edge.Cuts is non standard, and probably requires human intervention from the PCB manufacturer.
I guess the best compromise is to only put the outlines on Edge.Cuts, and draw the V-cuts on one of the user layer and add a note which file is for the V-cuts.
V-cuts would be pretty easy to implement as a pre-defined layer name in KiCad (and also set the .Filefunction during Gerber creation). But KiCad also does not have built in support for panelization, and V-cuts is probably low on the priority list.
I did a few attempts to search for V-cuts on gitlab, but apparently the search function chokes itself on hyphens. (Bit of bollocks that English apparently has an “Em Dash” “En Dash” and “Hypen”, which all look like the minus sign).
I did one board with our favorite low cost place in China. I put it on edge cuts with a note that said V-Score and got what I wanted.
This was a board I could put on one half of the 100X100 layout so I did my design, copied it to the other half and added the V-Score and ignored all the warnings I got. Lots of air wires at this point. But so what? The actual board design was done.
Still no ignore flag for DRC?
Sure there is. “Board has malformed outline” and “Segment on Edge.Cuts” can be set to ignore just like any other DRC violation.
How did you create the note? Drawing that as text on Edge.Cuts would be dubious at best. Did you mail it? Put it in an extra text file?
I also had a brief look at JLC PCB Capabilities and it’s not very clear, but it looks like that putting extra lines on Edge.Cuts is their normal way for specifying V-Cuts.
Hmm… Can’t find the project. But, now that I realize how old it is at this point, I probably shouldn’t have said anything. I don’t think the note was on the edge cut layer, but, this was version 4/5 of Kicad. So like I say, forget I said anything. Other than JLC didn’t seem to mind and understood what I wanted.
