I am trying so set up design rules for a microwave board and needs to set strict rules on microvias between different layers. Thus, I did the rule:
(rule "L1 -> L3 uvia"
(constraint hole_size (min 0.175mm) (max 0.175mm))
(condition "A.Type == 'Via' && A.Via_Type == 'Micro' && A.fromTo('L1.Cu','L2.Cu')")
)
The problem is that when I have the A.fromTo() in the condition, it does not trigger on this micro via:
Have I misunderstood the fromTo?
Thanks,
Robert
A solution is to use something like:
(condition "A.Type == 'Via' && A.Via_Type == 'Micro' && A.existsOnLayer('L1.Cu') && A.existsOnLayer('L2.Cu') && !A.existsOnLayer('L3.Cu') && !A.existsOnLayer('L4.Cu') && !A.existsOnLayer('L5.Cu') && !A.existsOnLayer('L6.Cu')")
Does not explain the use of the fromTo-function, but is awork-around.
From | | | Documentation | KiCad under Custom rule syntax in table Expression functions at fromTo('x', 'y')
Returns true if the object exists on the copper path between the given pads. x and y are the full names of pads in the design, such as ‘R1-Pad1’.
Looks like fromTo() checks for the connected pads rather than the layers.
Maybe you could try Layer_Bottom and Layer_Top ? Maybe something like
(version 1)
(rule "L1 -> L3 uvia"
(constraint hole_size (min 0.175mm) (max 0.175mm))
( condition
"A.Type == 'Via' && A.Via_Type == 'Micro' && A.Layer_Top == 'L1.Cu' && A.Layer_Bottom == 'L2.Cu' "
)
)
? (assuming you named the layers L1.Cu and L2.Cu, which isn’t the default of In1.Cu and In2.Cu)
(Edit: Corrected example)
Thanks. That sounds like the right thing. Tried it, but does not work. This looks like a bug actually. From the constraints report:
Checking rule L1 -> L3 uvia hole size: min 0,1750 mm; opt undefined; max 0,1750 mm.
Checking rule condition "A.Type == 'Via' && A.Via_Type == 'Micro' && A.Layer_Top == 'L1.Cu' && A.Layer_Bottom == 'L2.Cu'".
Condition not satisfied; rule ignored
What version do you use? I use a older 7.99 Version, i get »No errors found.«
Which layer is L1.Cu and L2.Cu? Is L1.Cu above L2.Cu? If not, you may have to swap Layer_Top and Layer_Bottom in the rule?
Maybe you should check if you should open a GitLab issue report.
I use 7.0.8 and the idea is that I want to generate an error. I have a via that is work. I am kind of building a test-board at the moment with all rules and I have a via that is violating this rule, but it is not caught with the Layer_Top… solution. It is however captured with the existsOnLayer… construction.
I was talking about the rule checker errors, not about the DRC violations in the PCB.
No error in the Custom Rules Editor:
The Vias that violate that rule are reported:
Hi,
fromTo can be used to define topology of a connection (eg. fromTo('IC1','IC2') would take all paths between pins of IC1 and IC2 into consideration. It was meant to define length constraints. There is no dedicated constraint/expression for blind/buried vias layer ranges yet - for the moment I suggest using the workaround proposed in this thread. Full pad/via stack definition will be coming to KiCad at some point in time.
Tom
This is strange. Actually my 7.0.8 KiCA on Windows does not catch that when using the Layer_Top… construction?
Can you upload a project with that problem (including all files necessary to open it)?
I have the same problem with your project. Maybe you should now open a GitLab issue (in case it is not already done).
It’s failing to take custom-layer names into account for Layer_Top and Layer_Bottom. It should work if you use the canonical layer names (“F.Cu” and “In1.Cu”).
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