Upgraded PCB from v5 to v8 errors and warnings

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Hi all,
I have a designed PCB that I am trying to upgrade from v5 to v8. This is a card edge design - probably important to clarify that, as I think otherwise it’s difficult to understand the following - and initially, it seemed to be unable to successfully create good gerbers under v8 due to the board outline cutting into the card edge footprint. Under v5 this was not an issue, the Edge.Cuts lines would cut with no problem.
There’s a bunch of other errors and warnings that get triggered under v8, but I really only care for being able to create the gerbers for correct fabrication. I tried shrinking the individual pads on the card edge connector footprint, and no matter what I do, it doesn’t seem to be able to generate the cuts.
I can probably upload the errors/warnings log, but not sure what else I can post on here to assist in getting useful input. I include some pics below that show some of the conditions that trigger these issues.

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Thank you all for your input!

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I should also probably clarify that the above images are of already shrunk individual pads on the footprint. But no matter how much I shrink these - and there’s a point where I’m not sure I’d have pads large enough to establish good contact - the design is unable to cut properly all those indents visible above, such as that one from between the 15 and 16 pads.
One thing I’m not sure what it is is the red thin line outline around the pads. Probably trivial, but can anyone point what that outline represent and how to adjust it (or remove it)? I suspect that’s part of the problem here.

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Ok, just to confirm, so each finger on this connector really has it’s contour cut out on the Edge.Cuts layer? (This is quite unusual).

KiCad has gotten much more powerful over the last couple of years, many features have been added, and among that is improved DRC and flagging of errors. KiCad V8 now checks a lot of thing that KiCad V5 simply was not aware of, or were badly implemented back then.

We can give the best advise if we have the most information. Without even the text of the errors we are just guessing. The best is if you create a simple test project which has this footprint on it, (prefereably connected to “something” even a few resistors is just fine) and then upload this test project. This allows us to fully analyze what the problem is, and also to do some quick experiments for determining the best solution. KiCad V8 will flag copper to close to the PCB edge as a DRC violation (You can set this in PCB Editor / File / Board Setup / Design Rules / Constraints / Copper to edge clearance. But I do not know why this would prevent creating (proper) gerbers. It just generates DRC violation messages. With a test project we can check for such things.

I may be color blind, but I see red pads with a purple outline. This purple outline likely (again, I’m guessing by lack of info) is from solder mask expansion, You can verify this by hiding the F.Mask layer, and it probably has nothing to do with your problems.

I am puzzled why so many people apparently do not even read error messages (nor attach them to posts) KiCad generates all that text for a reason. It has useful info! On top of that, you can click on DRC violation messages to see where it is on the PCB (although KiCad is guessing for locations on some of the DRC violations).

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Paul,
(assuming here… isn’t that like a faithful sign?)
I’ll attach warnings and errors logs, but, inasmuch as I’m overwhelmed by them, I didn’t want to add a ton of information here to what I hope it’d just be getting an old project successfully upgrading and moving along to “fabrication”-ability. I was hoping something simple may transpire - and something I didn’t think of - and I could salvage this project and be on to the new ones. There’s plenty of them.
I’ll also get crucified for this, but this is an older project I created in the PCBNew standalone app (created in v5, now migrated with limited success to v8). May not be relevant for getting this unstuck, but just to set the expectations.

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Such an error report is just a simple text file and you can open it with any text editor. If you can’t open it, then maybe your file associations are set up weirdly.

Your DRC report does have some info you may consider proprietary, such as the project name. It is an “extender” for some gadget. :slight_smile:

DRC found 176 violations. Wading through 700 lines of text without context is more overwhelming for me then for you (Inside KiCad you can resolve whole error classes and make the list shorter quickly to see what is left).

Using Save as as I suggested, and then delete everything except the connector, is not such a big tasks and also removes proprietary info.

[invalid_outline]: Board has malformed outline (self-intersecting)
    Local override; error
    @(297.6885 mm, 208.2500 mm): Segment on Edge.Cuts
    @(297.6885 mm, 208.2500 mm): Segment on Edge.Cuts
[invalid_outline]: Board has malformed outline (self-intersecting)
    Local override; error
    @(297.6900 mm, 208.2500 mm): Segment on Edge.Cuts
    @(297.6885 mm, 208.2500 mm): Segment on Edge.Cuts

Malformed outline / Self-intersecting is a serious error. (And there are more of them, at least 7). KiCad V8 has: PCB Editor / Tools / Repair Board, but would not trust it to fix issues in a proper way. To recommend a proper way, I would have to see the Edge.Cuts vectors. With a malformed outline the Gerber output will also be faulty.

There are some 160 DRC violations in the form of:

[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(168.3400 mm, 61.5600 mm): Track [<no net>] on F.Cu, length 142.8800 mm
    @(168.3400 mm, 204.4400 mm): Pad 7 [<no net>] of REF** on F.Cu
[solder_mask_bridge]: Front solder mask aperture bridges items with different nets
    Rule: board setup solder mask min width; error
    @(168.3400 mm, 61.5600 mm): Track [<no net>] on F.Cu, length 142.8800 mm
    @(168.3400 mm, 61.5600 mm): Pad 7 [<no net>] of REF** on F.Cu

This is probably a simple thing to fix them all. but without the PCB I can not see the details of what exactly causes all these violations. All seem to be between a track with a length of 142.88mm and a pad.

Oh, sigh, another attempt to create a PCB without a schematic. There are a lot of difficult ways to fix this in KiCad, and there is a simple way to fix it. The simple way is to draw the schematic.

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Thank you for all that.
I think the malformed outline / self-intersecting is the one category of errors that breaks the board.
I have two options:

  • restart the project and import the card edge footprint (1), and the outline of the board (Edge.Cuts layer linework) (2) into a fresh design. This would allow me to built this ground up with a schematic, etc. Also, better and leaner mitigate the errors and warnings. Frankly, I think some are just because of jumping this from v5 to v8.
  • just sort out the MO/SI errors. To this end, what would be an easy way to sort this out? I keep on trying to make the line end snap on each other to close the outline and they don’t seem willing. In Preferences - Editing Options - Magnetic Points everything is set to Always.
    I enclose the snip of one such point where there’s as much alignment of the corner of that cut as I can make it.
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Well, I seem to have sorted out the MO/SI errors. I decided to just redo the trouble lines - delete, then redraw, having this time the benefit of being able to snap on the end of the other segment - and the 3D viewer now is able to correctly outline the board with all the indents on the board outline.

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Fixing a handful of small issues is better then redoing the whole project.

Also, every now and then, put i some effort in what the error messages actually mean and how to fix issues. This does take some conscious effort, maybe it seems more trouble then it’s worth, but it broadens your general knowledge, and if you have done such things a few times, then it becomes easy and logical and you can fix issues quickly.

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I agree. The major roadblock was the “MO/SI” errors, which I did read carefully, distinctly realized they are the core cause of my predicament, and only fixed successfully due to my decades-long experience with AutoCAD and the rest of that design environment. Redoing the lines - realizing trying to fix them butts against the capabilities of the software - is what got the project unstuck.
Paul - thank you very much for your continued generous support!

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I don’t know what a MO/SI error is (I first assumed it was a typo), but apparently you have sorted them out so I guess it’s OK for you :slight_smile:

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MO/SI = “Malformed outline / Self-intersecting,” so the dead stop roadblock in my case.

Everything else was less critical. How I was seeing this is trying to generate a 3D view of the board and it’d fail to create all expected nooks and crannies in the board, and also flagging the error on top of the 3D viewer.

My other point was that sometimes it’s better to redo, than trying to fix something. Those lines were as correct as they could be, but I think the upgrade from v5 to v8 somehow broke them. Redoing them with a positive “snap” on the end of the prior segment “persuaded” the program those are legit continuities of the board outline and allowed the gerbers to generate correctly.

None of which means I appreciate any less your support paulvdh. It’s always been as generous as it could be. One of the parts I’m embarked on here is to better learn the program. That can be frustrating when you see 180 errors thrown at you and it’s certainly disheartening for the “average experienced” (in an optimistic reading… ;)).

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Most of the fingers in your screenshot do not ave DRC error arrows. The malformed outline has nothing to do with those fingers. I have seen some issues caused by rounding errors. To examine that you would have to upload both the old V5 and the new V8 project to compare them (or you may do that yourself). But because of your reluctance to make a simple test project with just the footprint & outline this is unlikely to happen. Maybe some other test case will present itself sometime.

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“But because of your reluctance to make a simple test project with just the footprint & outline”

If you mean my “option 1” in my set of options above, I’m not at all reluctant. It’s just a matter of fixing this v5 file, sending it out to fab today/Sunday (production will start during my evening here), and then I can take all the time I may or may not have (my actual day job has me dedicate some substantial time this weekend to work projects) to recreate a better formed project for this. Differently put, I can do option 2 now, be on my way with my project, and hope very soon I have an opportunity to get to option 1.

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Yes, reluctance. You even deleted your own post with the error report. That is of course your prerogative but your quest for secrecy makes it more difficult to help and has made this thread twice or three times as long as it could (should?) have been.

I think enough is said about this topic.

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I agree. Everything after the post above marked “Solution” was unnecessary.