Hi, upon upgrading my project to KiCad 7 I ran into troubles with thermal reliefs upon performing DRC. There are now several “Error: Thermal relief connection to zone incomplete” errors in my PCB and while I can understand some of those errors, others are rather strange.
Another case (ignore that the ground area is rather pointless in this case, but it was generated automatically). While laying out the components I added vias to all Vcc and GND-pins and connected them to the pins. Some of those become redundant with ground pouring obviously. However KiCad adds a thermal relief to pin 2 of both capacitors but doesn’t count the traces between the pads and the bias as thermal reliefs. How to handle such a situation ?
Somewhere (I have no KiCad here) you can specify the minimum relief connection count and about each connection having less of them you will be informed by DRC.
Edit.
I replied before you added pictures.
In last picture I suppose there is only one relief connection and the second is track that is not counted as relief.
Hi Piotr, the setting is in the board settings, but I assume that reducing the minimum number of thermal reliefs doesn’t really solve the issue as thermal reliefs are useful, especially with larger pads.
Before V7 (or V6 - I’m not sure) you didn’t had this error/warning so you can get to previous behavior by reducing it to 1.
I run DRC when my PCB is practically finished. You can not reduce that number to be warmed about such situations and after looking through them reduce the number to switch off these messages.
It looks to me like you may have to much space between the pad and the pour, I would remove the extra via’s for the moment and decrease the distance from pad to copper pour. I don’t know what it should be but your PCB manufacturer will tell you minimum distances so go with that, then the copper should go where it needs to. You have two via’s on the ground pads and you have connected them with a trace, this will not be needed or can be added later Not sure if any of that made sense as its difficult to describe what I see !
I understand the discussion above, but I do not see why I am getting this error in the configuration below. I see two spokes, and they are not sharing a corner, yet I still get the violation.
Are both sections of that GND plane connected to the rest of the GND plane via other means, or is one of those sections only connected to the rest of GND via a single thermal spoke?
@paulvdh I think you have it. This is a through hole with a connections to the back layer via two spokes, and the back layer is almost a complete pour. But yes, I confirm it wasn’t counting one of the top spoke because the pad it connected to was an island, if I add a via to the back GND on this island, the error goes away.
Is there a electro-mechanical reason a through hole should not count as much as a via? Or is this just a glitch?
Oh, you mean the pad hole itself is plated. I thought you had another hole somewhere in the isolated island that might not be plated.
In that case the current can go through the pad hole, but it still can’t go through one of the spoke (as it has nowhere to go after getting to the isolated island). So you still have only a single spoke connecting the plated-through-hole to the zone on that layer.
(For what it’s worth, 7.99 will tell you which layer has the problem, but 7.0.x doesn’t.)
Not sure if any of that made sense as its difficult to describe what I see !
