Hi, I am very new into the PCB design and I was trying to adjust my board setup design rules for the JLCPcb 2 layer constraints but the constraints on their website and KiCad are a bit different, can someone guide me on this ?
Thanks
When I started out I underthunk it, submitted and continue to submit designs with the default KiCad settings to various fabs and the results are fine. But then I don’t do anything complex just hand soldered boards. The only time I got a query from a fab was when I created a microvia by accident. I do have a power netclass with wider tracks though.
Up to you whether you want to blithely follow my amateur folly. 
Ideally in some future version fabs could publish their settings as files which are read into KiCad.
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May I ask what is the netclasses for? And is this for 2 layers or 4+ layers because they are different
netclasses in KiCad can be ussed to group nets that have the same trace/via settings
These rules already exist in fact, which are the factory’s ultimate capabilities, and their rules can be moved from project to project, and they can change depending on the device.
Of course they exist. This is the example from this forum’s user repository:
And there is a few more on Github.
I use only 2 netclasses. One is Default and one is HV (from High voltage, but at my PCB it means 24V). For HV netcalass I specify bigger clearance (0.4mm why for the Default 0.2mm).
When you will have at PCB galvanic isolation you can put isolated section nets into their own class and then probably (I have never tried it) define Design Rule to preserve big distance between nets from main and Isolated sections.
You can’t simple specify higher clearance for nets belonging to isolated section as it would mean also clearance between them.