I am looking into a design rule and confused on the numbers. Attached image. I see that the min drill diameter is 8 mil. In the KiCAD design rule > global design rule > via section, where should I put that 8 mil? At ‘diameter’ or at ‘drill’?
I think I should put that to the ‘drill’ section. Am I right? So then what should be the ‘diameter’?
Also, where do you specify min spacking?
Yes, 8mil (0.2mm) is the minimum drill size so should go in “Min via drill diameter” in the Global Design Rules tab.
The actual via size is the via drill plus annular ring size which isn’t in your list of dimensions. Annular ring size is the thickness of the copper around the hole and is the smallest you can have for a via or a plated through-hole pad. Normally your board house should specify this as well. Typically it is specified as the width of the copper around the hole, so for an annular ring of 2mil (0.05mm) your via size would be 12mil (0.3mm) which is copper + drill + copper. It depends how critical small vias are to you, you should be safe with an annular ring size of half the track thickness but usually worth checking.
Thanks Nathan.
What about min spacing? Where should I specify that? Is it on the “Clearance” column in the “Net Classes Editor” tab.
Spacing refers to the clearance. You will be able to set that on a net class basis (and need to at least have the “default” clearance set to 6 mil in your example).
So the min via size=min drill size + 2X annular ring size =8mil + 2X2mil=12mil?
My board house is saying that for class 2 it can be 5 mils annular ring. So that means the min via size is = 8+ 2X5=18 mil?
That is correct.
And remember, the board house sets the absolute minimum they guarantee. If you are not packing components in super tight, you can always user larger. I refer to this chart of standard PCB drill sizes to pick something the fab is likely to have and then choose the appropriate annular ring based on minimums.
If you’re using a board house with similar dimensional restrictions, you can always check the design with a 3rd party tool like FreeDFM from Advanced Circuits.
How do I specify ‘Impedance control’ & ‘Impedance variation’ that is mentioned in the design rule table above?
You probably don’t need to. Unless you’re doing RF or high speed digital (100MHz or more) on the PCB it is unlikely to affect you. Properly specifying impedance and board stack ups can require a completely independent piece of software and a new set of design files if you’re doing something serious.
I am doing RF. Won’t use ‘impedance variation’ due to cost but need to use impedance control. Based on your reply in this thread, I assigned net class name.In the PCBnew, I can see those nets are assigned default net class.
Now I am a bit confused when you said “…assign them to a custom net class which has appropriate thickness/clearance for 50Ohm at your chosen frequency…”. So I should change the trace width and clearance of this new class that represents 50Ohm line? What should be the trace width and clearance? How do I calculate that?
There’s a tool called PCB calculator in the KiCAD launcher screen (5th button along on my version). Run that and select the “TransLine” tab. This gives you a whole heap of different options depending on what type of transmission line you are trying to match.
The critical things you need to know (which I couldn’t see all of in your design constraint summary) are layup details. It says at the top that it’s a 4 layer board and its 1.1mm thick, but I don’t know where the internal layers are. In a basic grounded co-planar wave guide you have ground fill top and bottom and a trace with specific clearance and width running through the ground plane on top. To calculate the width and spacing though, you need to know how far to the next layer. I’d guess the inner layers are only 0.2mm from the outside but that can vary. Do you know what kind of transmission line you need? Do you know what frequency the line will need to work at?
