I have a very simple board, as below. The bottom copper layer is filled zone on the GND net, the vias are GND net, the SMD pads are GND net. So the rats nest resolves, and DRC passes without errors or warnings.
However, when I export the Gerber files and upload to JLCPCB DFM, the DFM tool warns of “isolated unconnected vias”. Screenshots below, what am I doing wrong please?
What you see in exported gerber?
This is what I see in the Gerber file viewer of the DFM. To me it looks sensible, but I am very new to this so maybe there is something obviously wrong?
I don’t know how to interpret it. Perhaps, kicad’s gerber viewer would be better for this.
Can you disable scetch view? This might be more informative
Thank you. I have put the complete KiCad project, and the Gerber file export here. (I couldn’t upload a zip file to the forum as I am a new user).
Gerbers look OK to me . . .
I would suggest your vias could be bigger and why do you need 0.2mm wide tracks ?
Did you send drill files with your Gerbers ?
Thanks @RaptorUK. The track width and via size are the KiCad defaults as I just wanted to create a quick project to demonstrate my issue.
I did include drill files, the complete Gerber/drill package was created by Bouni’s JLCPCB Tools plugin.
I have added the complete package that I am uploaded to JLCDFM here:
Thank you for you help, I appreciate it as I am completely stumped!
Still looks OK to me . . . contact them in their on-line Chat and ask for an explanation.
I experience this now and then and the boards were always ok. Btw, JLCPCB and NextPCB DFM act strangely at times. And they differ in their diagnosis as well.
I’ve been doing a bit more digging into this since JLCPCB aren’t currently answering their online chat. Referencing the image below, I can remove the warning by doing the following options in KiCad:
(1) A short trace on the bottom side from the via to the filled zone
(3) Making the filled zone smaller forcing me to run a trace from the via to the zone
I also tried making the filled zone smaller (2) with no other additions but unsurprisingly this didn’t change anything as it is really the original problem case.
I think the likelihood is the issue is with the DFM tool, but equally I am wondering if there are any setting in KiCad that could help eliminate this warning, since just ignoring warnings means maybe missing a real one…
It’s pretty clear that JLCPCB’s DFM tool is brain-dead.
It’s not smart enough to realize that a via doesn’t need a trace if it’s inside of a copper flood.
…and not even that for all such vias. Sporadically.
Thanks everyone for your input. I’m going to just ignore the warning, as much as that pains me!
