Tying layers with ground fails to carry ground

[fsonnichsen]

I have a 2 layer board. Both the top and bottom are ground filled. I have a few stray “islands” that do not connect to the ground. In order to remedy this I tried applying a GND via to the lower layer, expecting this to carry the ground from one to the other. For some reason this does not seem to work. This happens often.
Probably I am missing something here?

Fritz

![Capture2circuit_pulse2.zip (126.4 KB) |690x420]

[paulvdh]

Here is a screenshot from the bottom side.

The encircled area on the top is not connected to the section on the bottom.
To fix it, you have to remove the 3 tracks I’ve crossed through and put them on the other side of the PCB.

You should also take this in a more general sense.
Having both GND fill on Top and Bottom in little patches and attempting to stitch them together does not work very well. Your first goal should always be to have one GND plane and have it all over the PCB. Only then use via stitching to connect GND to sections that can not be done in another way.

[iabarry]

You need to add 2 more Gnd Vias to the right of Pin 1, the other below the gap in the GREEN GND. This will bridge the gap by connecting upper Green, to Red, to lower Green.
This will make DRC happy, but you should have more of these in strategic locations through the board. Alternately, reroute the green trace which separates the 2 Green GNDs.

[paulvdh]

I have edited your PCB a bit:

• Moved most of the green tracks on the bottom to the top.
• GND is now almost continuous on the bottom.
• Note there is now less GND on the top layer (Right bottom corner) but that does not matter.
• Added some via stitching to connect “corners” of the GND plane of the top to the (continuous) GND plane on the bottom, and some near SMT pads which are on the Front layer.
• Made GND connection on J1, Pad6 a bit thicker (30mil) and on both sides of the PCB.
• I also moved Net-(BATTin1-Pad1) to the top of the PCB. The reason is this that those tracks on the bottom prevented a current flow straight to the 3 power connectors on the “North” side of the PCB. That is more important then the slightly longer tracks for Net-(BATTin1-Pad1). If this net carries a lot of current, then add a small zone for it on the top side. It really is not important here to have a GND zone on both Top and Bottom here. One uninterrupted GND zone is much more important.
• I changed the Zone outlines. You put them directly over Edge.Cuts. I made much bigger pentagons of them. This has a few advantages:
  1. It is quicker to draw initially (coordinates are not important).
  2. A pentagon makes it clear that the coordinates are not important.
  3. Zones and Edge.Cuts items are now easy to select with single click.
  4. PCB edges are automatically clipped.
  5. If automatic clipping does not work properly, you see it instantly, especially when inspecting gerber files.

Notes:

• I also removed some files (mostly backups) from your project to make the .zip smaller. The zip file shrunk from 129 kB to 45kB.
• I also noticed you had a netlist file. This has been deprecated for several years now. Use Eeschema / Tools / Update PCB from Schematic [F8] instead.
• Via stitching on corners and near pads is a good rule of thumb. For a more thorough solution you have t analyze the directions of how the currents are flowing through the GND planes.
• I added a date to the zipped file in SO_8601 format. I do this often when making backups. It helps when keeping track of things, and zipped files with a date are always backups for me.

circuit_pulse2_2021-02-07T08:05.zip (44.0 KB)

[fsonnichsen]

Paul
thanks for all the work on this. I am still looking over your re-draft. It makes sense and I just did something similar on mine for comparison. The concept that you point out (making the GND plane as contiguous as possible) makes sense. Getting to that point is difficult at times but starting out that way goes a long way! (My original draft was fine but I had to add some things that messed it up).

Thanks again for all the work-
Still looking this over
cheers
Fritz

[fsonnichsen]

Barry (and Paul)-
One thing I don’t quite understand–(redoing the board is the right way to go but this question is academic regarding KiCAD).–
I had added a via from green to red just to the NE of the GND on pin 1 of the cap. It seems like this should have connected the two boards hence giving pin 1 a good GND (the green area is completely connected north of the divide). Am I missing something that is disconnected? Seems like this should have worked?

Thanks
Fritz

[paulvdh]

It’s probably the same issue as your first post in this thread.
“Green” zone sections are not always connected to “Green” zone sections, and ditto for “Red”.

This also makes no sense to me:

@fsonnichsen

It seems like this should have connected the two boards…

It’s just a single PCB, with two layers of copper???

About the continuous GND plane:
For a big part it’s for EMC compliance and EMI prevention. For signal frequencies above around 100kHz the return paths of all currents is through the GND plane directly beneath the signal track, because that is the path of least impedance (Induction increases with loop area). For low frequencies the restive path dominates. This is worth reading more about. Many books have been written about this subject, some youtube vid’s have nice simulations for current paths at different frequencies. Changing an existing PCB layout to make the GND plane continuous can be a bit involved, but your PCB was already quite close and I changed just a few small things. If you design according to this rule from the start, then it won’t take as much time. It also helps if you’ve built up some experience.

[fsonnichsen]

Paul-sorry for being vague here. First of all my statement should have read “connected the two PLANES” not “connected the two boards”.
The attached design is probably redundant but just to be sure it shows what I had been trying to accomplish by adding a via to stitch the 2 planes. For some reason this does not seem to work at times. If one of the planes is connected to a PWR-FLAG then the resulting stitched plane should equalize to that power to my understanding but this does not seem to always work.

Of course if neither plane is connected to the power the disconnect still stands. I don’t think there is a good way to test this-the “highlight net” highlights both connected and unconnected planes since the latter are nonetheless in the given net even if not connected.

I understand your comments on EMC. I think this was mentioned in a prior post. Somewhere here I have an old book that describes some of this and I need to re-read it. I get a bit lazy because a lot of my work is at low frequencies. Also I used to use 4 layers a lot–more than needed so I am trying to get more adept at planning 2 layer boards. Probably there are new books out there that I need to check on.

One thing I am short on is some good KiCAD board designs by experienced users to look over and get ideas on layout-I see a lot of simple/basic ones on the web but nothing more advanced.

Many thanks again for your help-

temp.zip (7.5 KB)

[paulvdh]

There is nothing wrong with your test project. Looks just fine:

I did click on Pcbnew / Edit / Cleanup Tracks and Vias, which merged some segments. but the board is DRC free. “PWR_FLAG” is only ERC (and thus Eeschema) related.

If you want to have a look at some more complicated PCB’s, then have a look at: https://kicad.org/made-with-kicad/ The Olinuxino PCB’s (lots of projects on github) are quite nice and there is also some phone development demo.

[fsonnichsen]

Thanks Paul.
yes-my example always does what is expected when you add or remove the via. but with more complex designs it does not. At any rate I will work towards initial good design to start (with a contiguous GND plane) and probably that will go a long way to solving the problem.

Thanks for the example–I was did not see them—lots of good examples.
cheers
fritz