I have two boards on one schematic and one layout. They are connected with FFC.
Pcbnew shows airwires between the two boards, for ground and for +5V. These are superfluous. How do I tell Pcbnew that the connection between GND and +5V is taken care of by the FFC.
Annotated screenshot:
After moving some components, the top board is not completely routed anymore. However, the issue existed before as well, i.e. when everything was routed.
You’ll need to name the nets differently on different board. Multiple boards are not yet supported. See: https://bugs.launchpad.net/kicad/+bug/1003227
Was thinking about this too, just wasn’t sure if that is the right approach.
Guess I would need to create custom power symbols then, e.g. BOTTOM_+5V and BOTTOM_GND. I wonder if that is worth the hassle. Maybe I’ll just ignore the airwires.
As a hack you can draw a 4 layer PCB, and put the “missing” connections on the not used layers. This does probably add some un needed via’s to the board though. Give those layers a desctiptive name though, and put some weird text on it so you do not send them accidentally to a PCB manufacturer.
Maybe you can make those connections to the THT connectors.
It is also a good idea to also add some via’s to the mechanical pads of connectors. This greatly reduces the chance of the pads getting ripped off the PCB if the connector is stressed.
Do you realize that your mouse bites stick out of the edge of the PCB when broken off?
The “vertical” parts of the isolation slots in the middle are also a lot thinner than the horizontal pieces. Are they wide enough to get routed?
Thanks for the suggestion, but I think it’s easier to just ignore the airwires.
Think this is a great suggestion!
Yes I know. In fact I skimmed through a blog article about mouse-bites that mentions this issue. But it doesn’t really matter here. In fact I’m thinking about changing to a single perforation. It’s an electronics kit, and users can break it apart themselves. Furthermore, the boards will be inside of an enclosure.
That’s because I was thinking about reducing the vertical slots from 2mm to 1mm once I have made a single perforation mouse-bite footprint.
What distance would you choose?
Board thickness will be 1mm, and assembly will be done by Seeed Fusion. (could send them an email now, maybe I’ll get a response tomorrow)
Why did you ask then?
PCB manufactures often have info on minimum slot width (thin fragile mill, slow = expensive) and thicker & stronger more standard mill sizes which are cheaper.
Seeed has quite some info on their site with tips and preferred practices. For example:
https://statics3.seeedstudio.com/fusion/ebook/PCB%20DFM%20V1.1.pdf
I wanted to see what options there are, and also it could’ve been that I’m doing something wrong. I appreciate your suggestions!
Was looking for information about tolerances some days ago, but now searching for minimum slot width seeed finally brought me to:
Concerning PCBA, I already went through a lot of info provided by Seeed.
Regarding slot width:
Minimum milling slot width: ≥0.8mm
Slot Tolerance (Mechanical): ±0.15mm
So I think 1mm slots in a 1mm board should be fine.
As well as the 4 layer suggestion above (2 non-plotted layers are for connections to pass DRC ), if you have a PCB that can break sometimes, you could also run traces across the mouse-bites to allow testing of the whole assembly before break-apart.
I’ve also seen test headers placed ‘outside’ the finished PCB outline using the same cut traces on break approach, which can help on very tight PCB designs.
I wonder if there is any danger of traces ripping off when trying to break through them. (guess not, just double checking)
Yes, you are right - traces can pull off but there are a couple of tricks to avoid this. You can neck down the track at the planned break line and/or introduce an angle in the track.
Just did a lot of routing and was thinking: Any of the hacks that connect GND between the two boards - either via break-away traces or via additional layers - is a potentially dangerous idea. These traces may contact a GND island on the other board, thus preventing DRC from reporting that. So the best idea still seems to be a separate net, e.g. GND-2 (and +5V-2).
I’m not following ? DRC will only not report, if GND touches GND, which surely is legal anyway ?
Some care might be needed if running multiple GNDs across many breakoffs, but the risk here is not a unwanted contact, but a chance the GND plane could split on one PCB, if the contacts do not ‘line-up’ with the cable alternative.
I’ve done this before and it’s worth it. Nice for the rule checker too.
That’s actually how I read @feklee’s message to be. The trace across the breakaways allows what would be a GND island when the boards broken apart appear to be connected to the DRC.
… but for that to be a real issue, you need more than one trace, you must have two, or more, and also have those not duplicated in the cable that replaces the break-off.
Where I’ve seen this done, there is usually a 1:1 replacement of the cable wires.
If someone pours a plane across the entire design, that’s up to them to check 
Yesterday, I created a project specific symbol library. Today I simply copied GND into it, as GNDB. The name of the power input pin I changed to GNDB. Accordingly I created a +5VB power symbol. These symbols I now use for the second board. DRC is happy, showing no unconnected nets. 
Watch out. With the Power Symbols, the net they connect to isn’t driven by the symbol’s value (name), rather the hidden pin name. Make sure you have changed both.
Ok. I missed that detail. Glad you knew about it before hand.
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