With such a big gate resistor the gate capacitance of the Fet charges very slowly.
I’m still trying to explain why the first two pulses are 38mA and 20mA, while it then settles on 16mA (In the previously posted screenshot). It must be some interaction between R1 and the gate capacitance.
Next thing is that after holgers changes, the parameters for the voltage source are now listed twice in the model. In the “Value” field, and in the “Spice_Model” field.
I don’t like legacy stuff, so I cleaned it up a bit with symbols from the Simulation_Spice library.
And exchanged the squiggly resistors for normal ones
The symbols from the Simulation_SPICE library look much better.
VJ is a parameter for the body diode in the MOSFET subcircuit. The manufacturer set it very high (likely a byproduct of curve fitting measurements). But if it’s set too high, the junction capacitance approaches infinity so ngspice limits it to avoid crashes/instability in the computation. It sets the limit at 1/FC where FC is another diode parameter and is set to 0.5 in this case (which is also the default).
Oddly, I’m not seeing this. If I download the ‘mister-sir.7z’ file, the alternate node sequence shows as 2 3 1, and my simulation output looks just like what your first screenshot in the quoted post shows.
Ah, yeah, that’s a holdover from v5 – the “Simulation_SPICE” library doesn’t appear to come with v5.
Ah, I wondered about that too. Thanks, Ste, for explaining!
But I am hoping, of course, to get an output more like what you have in your second screenshot. Hoping to get a chance to look more closely at this in the next few days and see if I can find out where things are going wrong.
Hm, if I change the node sequence to 2 1 3, I get what paulvdh shows in his second plot. After comparing pinouts again, this appears to be the proper alternate node sequence.
Why “oddly”? The first screenshot in that thread was with the faulty 2 3 1 node sequence and changing it to the 2 1 3 order did get me results that look correct.
When I lower R1 to 330 Ohm then Q1 turns on quite quickly, but you can still see a plateau on the gate (blue trace) caused by the miller effect. When the gate voltage is high enough for Q1 to start opening, the voltage on the drain starts dropping and this capacitor has to be discharged through R1. The gate voltage only starts rising further if the voltage on the drain approaches zero and Q1 is (nearly) on.
The curvy part on the green track is misleading. When Q1 is off and there is no current through D1, then the voltage over D1 is pretty much undefined, but with limits between +1.8V and -0.6V. A 1M resistor parallel to D1 pulls this voltage up to 3V3.
Apparently there are also two places where the alternate pin assignment can be entered (In KiCad V6). Schematic Editor / Q1 Symbol Properties / Spice Model looks like:
However, the Q1 / Symbol Properties also has an Alternate Pin Assignments tab page, and I have not done anything with that. I’m not even sure what it does or if it does anything in the ngSpice simulation.
Edit:
Oops I made a *&^%$#@! in the node sequence, and mixed a few up and this got me thoroughly confused, and I’ve been trying to correct this for the last 20 minutes…
Ah – never mind. I just misread your post, we did the same thing.
Time for me to bust out the Art of Electronics book again and read up on FETs, I think. Although I think I’ve got enough understanding now to get this up and running on the breadboard again.
So we have the sequence drain, gate source in our model.
The transistor symbol is
with drain at node 2, gate at node 1, source at node 3.
To adapt the symbol’s node sequence to the model, and thus tell ngspice which Eeschema node is connected to drain, gate, source, the alternate node sequence has to be 2 1 3 in the Spice Model Editor field
