Seems to be a Debian problem.
On (x)ubuntu 6.0 has been available for months, PPA:
ppa:kicad/kicad-6.0-releases
Looks like I’ll need to update to v6 to do that – working on that now. Debian is a huge pain on that front, but I’m stuck with that for now.
Debian places a strong emphasis on system stability, which I didn’t realize when I installed it basically means running ages old packages all the time. 
Working on getting v6 so I can at least eliminate old bugs as my source of problems.
I like Debian very much, but I do not see it as a “usable” user friendly distribution. I see it more as a distribution that is mainly maintained as a foundation for more user friendly distributions. Debian is also very strict about “non-free” content (partly?) for this reason.
Maybe Debian also fits well for servers, where stability is more important than new features.
I can’t stand the colors and weird menu of Ubuntu, and don’t really trust Canonical either, so I settled for Linux Mint as my daily OS with a pretty simple Xfce as desktop. I find Mint very user (even beginner) friendly. It “Just Works”, both on 10 year old hardware, and on my new Ryzen 5600G and 107cm 4k monitor. Installation from USB stick takes about 5 minutes. (10 to 15 on older hardware). Why do you feel you’re stuck on Debian? A partition is easy to shrink with Gparted, and Linux distributions usually tolerate each other well. If you’ve got a free SATA port (or fast USB3) you can even install another linux distribution on a separate storage device and use your BIOS to select a boot drive. Mint is distributed as Live distribution, so you can test drive it directly from an USB stick. (I think most distributions do this these days).
The sallen_key demo is also available for KiCad V5. Possibly you have to install the KiCad_demo package separately to get them. Just do an apt search kicad to see what else is available. I do seem to remember I had to fiddle a bit with it to get it to work on KiCad V5, but I can’t remember details anymore.
6.0.4 is available in Debian backports.
There is eternal tension in distros between stability and new features/applications. It’s not just a case of new versions of applications are discouraged, it’s also that new versions may rely on newer dependencies (e.g. libraries) and upgrading those might put basic applications at risk of malfunction. That’s why there are so many workarounds: spinoff distros (e.g. those that use bleeding edge branches of Debian), PPAs, backports (someone has to do the work to adapt to older dependencies), Flatpaks, Appimages, virtual machines, multiple OS booting, etc. It’s bad enough when it’s one’s own machine, but the solutions may be more limited if it’s the company’s machine.
Anyway all of us have to find a comfortable spot in the spectrum. Some people chase distros and love to dodge rotating blades. Some are very risk adverse (“what do you mean I can’t run the latest Firefox on my XP?”).
Do you consider connecting XP to the Wickedly Weird World is risk adverse?
You probably typed a bit too fast there
Irony often seems to fail on forums. 
I think the risk there was the discomfort of revising their habits. 
As with a lot of things the vantage point changes the assessment. For your accident insurer the risk is that you will make a claim. For you the risk is that their payment may not cover your loss.
Back to the OP’s problem:
This is what I had to do, starting with the project provided:
V1:
ac 3.3 sin(2.5 2.5 38k 0 0) →
dc 0 sin(2.5 2.5 38k 0 0)
put into the ‘value’ field
V2:
dc 3.3
put into the ‘value’ field
.tran 1u 1m → added as text box
model for the diode added (chosen arbitrarily)
SNAPled150.mod
node sequence 2 1
spice transistor model:
not type bipolar, but type subcircuit
node sequence 2 1 3, not 3 2 1
mister-sir.7z (3.9 KB)
Edit: Updated to the correct node sequence 2 1 3
2 Likes
Holger is pretty much the most knowledgeable person concerning ngSpice here on this forum (he maintains the ngSpice software itself). and with his modifications, the mister-sir.7z file at least does “something”, see screenshot for current though D1:
Edit: This screenshot is with a faulty 2 3 1 sequence:
I had a look though his changes (also neatly provided in an extra text file (“steps_done.txt”), and I did not understand the changes to the node sequence he made. So I turned them to “2 1 3”, and this increased the current through D1 by about 4 orders of magnitude:
Then, reducing R1 to 1k creates a flat spot of 70mA though the led when the MOSfet is fully open, and this makes sense to me.
Edit:
I made some *&^%$#@! in the alternative node sequence. “2 1 3” is correct.
Oh, sheesh, that’s what I was stuck on. Thanks! Can’t believe I didn’t notice the first line of the spice model reads “.SUBCKT”
And that’s what I was hoping to solve! I figured one of my resistor values had to be off – the LED output on the breadboarded circuit was way too weak.
I was curious enough to play a bit more with it. so I changed the simulation parameter to:
.tran 100n 200u
To enhance the time resolution a bit and have less repetitive signals at the end and then re-ran the simulation, but this did not work. The time scale keeps on the first milli second. I have to close the simulation window and open it again (and re-run the simulation again) for these time parameters to take effect. This smells like a bug to me.
With such a big gate resistor the gate capacitance of the Fet charges very slowly.
I’m still trying to explain why the first two pulses are 38mA and 20mA, while it then settles on 16mA (In the previously posted screenshot). It must be some interaction between R1 and the gate capacitance.
Next thing is that after holgers changes, the parameters for the voltage source are now listed twice in the model. In the “Value” field, and in the “Spice_Model” field.
Then I saw the description of the pspice library:
Legacy pspice symbol library.
I don’t like legacy stuff, so I cleaned it up a bit with symbols from the Simulation_Spice library.
And exchanged the squiggly resistors for normal ones
The symbols from the Simulation_SPICE library look much better.
Still one thing I do not understand, In the spice simulator there is a warning about:
Warning: xq1:md: junction potential VJ too large, limited to 2.000000
VJ is a parameter for the body diode in the MOSFET subcircuit. The manufacturer set it very high (likely a byproduct of curve fitting measurements). But if it’s set too high, the junction capacitance approaches infinity so ngspice limits it to avoid crashes/instability in the computation. It sets the limit at 1/FC where FC is another diode parameter and is set to 0.5 in this case (which is also the default).
Oddly, I’m not seeing this. If I download the ‘mister-sir.7z’ file, the alternate node sequence shows as 2 3 1, and my simulation output looks just like what your first screenshot in the quoted post shows.
Ah, yeah, that’s a holdover from v5 – the “Simulation_SPICE” library doesn’t appear to come with v5.
Ah, I wondered about that too. Thanks, Ste, for explaining!
1 Like
But I am hoping, of course, to get an output more like what you have in your second screenshot. Hoping to get a chance to look more closely at this in the next few days and see if I can find out where things are going wrong.
Hm, if I change the node sequence to 2 1 3, I get what paulvdh shows in his second plot. After comparing pinouts again, this appears to be the proper alternate node sequence.
Why “oddly”? The first screenshot in that thread was with the faulty 2 3 1 node sequence and changing it to the 2 1 3 order did get me results that look correct.
When I lower R1 to 330 Ohm then Q1 turns on quite quickly, but you can still see a plateau on the gate (blue trace) caused by the miller effect. When the gate voltage is high enough for Q1 to start opening, the voltage on the drain starts dropping and this capacitor has to be discharged through R1. The gate voltage only starts rising further if the voltage on the drain approaches zero and Q1 is (nearly) on.
The curvy part on the green track is misleading. When Q1 is off and there is no current through D1, then the voltage over D1 is pretty much undefined, but with limits between +1.8V and -0.6V. A 1M resistor parallel to D1 pulls this voltage up to 3V3.
Apparently there are also two places where the alternate pin assignment can be entered (In KiCad V6).
Schematic Editor / Q1 Symbol Properties / Spice Model looks like:
However, the Q1 / Symbol Properties also has an Alternate Pin Assignments tab page, and I have not done anything with that. I’m not even sure what it does or if it does anything in the ngSpice simulation.
Edit:
Oops I made a *&^%$#@! in the node sequence, and mixed a few up and this got me thoroughly confused, and I’ve been trying to correct this for the last 20 minutes…
Ah – never mind. I just misread your post, we did the same thing.
Time for me to bust out the Art of Electronics book again and read up on FETs, I think. Although I think I’ve got enough understanding now to get this up and running on the breadboard again.
Thanks, all, for your help!
Same for me!
2 1 3 is the correct node sequence. I have updated my original post.
The subcircuit transistor model states:
.SUBCKT irlb8721pbf 1 2 3
**************************************
...
* External Node Designations
* Node 1 -> Drain
* Node 2 -> Gate
* Node 3 -> Source
So we have the sequence drain, gate source in our model.
The transistor symbol is
with drain at node 2, gate at node 1, source at node 3.
To adapt the symbol’s node sequence to the model, and thus tell ngspice which Eeschema node is connected to drain, gate, source, the alternate node sequence has to be 2 1 3 in the Spice Model Editor field
1 Like