Running 9.0.4
Teardrops for tracks only appear to work if the tracks join end to end, not if they connect like this (e.g.):
I’ve always “filleted” this type of connection in the past by drawing short track segments, but DRC and “Cleanup Tracks and Vias” don’t like me doing that. Can this be enhanced?
Thanks
David
Why do you want to do such a thing?
30 years or so ago, there were some rumors about “etching traps” in corners, and If it was a valid concern back then, it would have been so only with low quality factories. But 30 years is a long time. As a result, it’s just a waste of time to attempt to pay attention to such insignificant details. “Cleanup Tracks & Via’s”? Sure, it reduces vector count, which also makes following edits easier, but those corners are not relevant.
I do similar. Unless I need to go smaller, I generally use 8/8 trace/space as default so I also do things make my footprint pads with a bit smaller corner radius than default such that I can exit on a 45 0603 and larger without leaving tiny chinks and divots.
Sure, it doesn’t really matter a whit, but it looks much better and more ‘polished’ IMO. PCB layouts used to be called ‘PCB ArtWork’ and I’ve been doing it since before CAD tools existed by burnishing dollies and laying tape on Mylar. I still have that mindset when I route. I take pride when my designs both work well and look good (IMO) doing it even if anyone else could care less about such details. I see many layouts that trigger my pedantic OCD with hinky-jinkey pad escapement, off angle t-junctions, messy routes, etc, etc. Often I look back at my own Artwork and spot some detail that bugs me I didn’t see it sooner.
And no, I don’t think KiCad will do these pedantic details for you automatically. My old tool (PADS Layout) didn’t either. I don’t recall KiCad ever removing my extra bits of intentional redundant segment detail polish with its (user controllable) track cleanup routines nor any problems with its (user controllable) DRC checks related to such detail polish.
It’s not about etching traps, it’s about mechanical stability. every wire transition, doesn’t matter if it is from wire to pad or like in the picture above a wire crossing, creates weak points which can cause the wire to break off under stress. Especially for designs where high mechanical loads can be expected on a PCB having these points taken care off automatically and not manually as it’s the case rn would be great.
Sure, I agree with that near connectors, Especially heavily stressed ones such as PC104, and similar such as the Raspi 40 pin, and also screw connectors which invite pushing on the PCB (always good to keep that in mind when designing the PCB mounting system). But find it hard to believe this is a generic issue for T-splits, especially when all tracks are of similar width. But I’m split between knowing there is a lot of parroting on the internet, and not being able to debunk everything myself. KiCad V8 does have: PCB Editor / Edit / Edit Teardrops / Scope / Track to Track and I had to experiment a bit to get that to do anything. It only works when tracks are of dissimilar width. If it’s a real issue, then making a feature request to improve KiCad’s teardrop algorithm for T-splits would be a good idea. (It may already exist, have not checked gitlab).
It’s definitely not a generic issue, 99% of designs will not run into problems because of this. It really only matters in high intensity vibration/force deployments of PCBs, where the whole or part of the PCB are exposed to significant stress.
