Track not being able to route horizontally

I have a bunch of Relays that I’m routing vertically. I want to route very wide lines (>20mm) between them. I’m running into an issue where the router is trying to avoid a certain part of the footprint instead of just going from left to right:

I solved this by using copper pours, but they are tedious to work with (have to change net class manually, doing that for 9+ connections on 4 layers is very tedious.) Also it doesn’t “block” that space so I could accidentally route through it another trace.

If I could just use a 30mm left to right that would make it a lot quicker.

Is this somehow an issue of the footprint?

What KiCad version are you using?
Post full version from … / Help / About KiCad / Copy Version

If you post a smallish PCB here with at least one of the offending relay’s and some surrounding components, I’ll have a look at it. A screenshot does not say much.

See if this helps. Though, just looking at what you are doing having the extra copper of a pour might not be a bad way to go even if it appears to be over kill. :wink:

I added a small pcb with two footprints on it.

Changing to “highlight collisions” gives me this screen, but I couldn’t finish the track over the collision.
image

test.kicad_pcb (8.3 KB)

My Kicad Version:
Application: Pcbnew
Version: (5.1.6)-1, release build
Libraries:
wxWidgets 3.0.4
libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.71.0
OpenCASCADE Community Edition: 6.9.1
Curl: 7.66.0
Compiler: GCC 9.2.0 with C++ ABI 1013

Build settings:
USE_WX_GRAPHICS_CONTEXT=OFF
USE_WX_OVERLAY=OFF
KICAD_SCRIPTING=ON
KICAD_SCRIPTING_MODULES=ON
KICAD_SCRIPTING_PYTHON3=OFF
KICAD_SCRIPTING_WXPYTHON=ON
KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
KICAD_SCRIPTING_ACTION_MENU=ON
BUILD_GITHUB_PLUGIN=ON
KICAD_USE_OCE=ON
KICAD_USE_OCC=OFF
KICAD_SPICE=ON

Edit: I investigated the footprint (thanks to the highlight collisions option) and found out there are small edge cuts under the big holes for the relay. Removing them solves the issue. Not sure if those where intentional but I don’t believe so.

Edge cuts in a footprint will cause this.
Your narrow slot holes look like they may be hard to make. What is the smallest router radius your vendor allows?
The smaller PCB pins could easily use round holes.

If you “un-fill” the pads (Icon at mouse cursor) then you can indeed clearly see the lines on edge.Cuts. And ofcourse, the router routes around items on Edge.Cuts.
image

I also agree with davidrsb. Specifications for minimum width of slots is much wider than the size for round holes. Pads 5 and 6 have a slot width of 1.3mm and that may be too narrow for a slot, so check this with your PCB manufacturer.

Great hint, thank you!

I checked with JLCPCB (our EMS isn’t clear yet) for example and they seem to have 0.65 mm for plated slots, or am I reading that wrong?

https://jlcpcb.com/capabilities/Capabilities

I will check about making the holes round nevertheless, might bring down costs.

Thank you guys.

I would proceed by using 30+mm tracks on 4 layers between the relays and connectors (100A) instead of the zones, because that ensures the tracks stay that wide. Or is there a better way to do that?

I also see the 0.65mm minimum slot with @ jlcpcb

100A is a lot of current for a PCB. My first guess for this relay would be that it is made for screw terminals, and not for a PCB.

For these kind of currents, you need all the copper you can get. So at least lay tracks on both side of the boards (You have to disable: Pcbnew / Route / Interactive Router Settings / Options / Remove Redundant tracks for this) and you likely also have to use thicker copper.

There is also a limit to the effective width of your tracks. No matter how wide you make them, at the end the current still has to go to the pad.
“pn 4 layers”? Multi layer boards often have very thin copper. Good enough for signal tracks and GND planes, but not for these high currents. For these high currents you want thicker copper on the outer layers.

Such high currents also easily cause heating, for example in the relay itself, and repeated thermal expansion and shrinkage may cause cracks in the solder over time.

If I use 4 layers with 105 um on the outside and 75um on the inside it should be fine. JLC can’t produce that but there are other manufactures who can. The relays are meant for soldering not screw terminals, couldn’t even get them on the board otherwise.

Good tip with the redundant tracks.

Another thing I just thought of.

Copper on the outside layers are reasonably effective heat sinks themself, which lower temperature differentials generated by the heat in the relay itself, and this may (or may not) have a noticeable effect.

For 100A PCB relays there probably is a section of PCB layout recommendations in the datasheet itself, or in a separate leaflet from the manufacturer. (Or from another manufacturer, the principles stay the same).

Current rating of inner layer copper is much lower than the outer layers.
I would focus on a two layer board with 2oz copper, using both sides.

Soldering the relay power terminal will be “interesting”

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.