I’m doing a board layout where I would like the traces to have 12mil clearance to reduce crosstalk, but they are connected to an IC where they will have less clearance than that between pins.
When I try and use the interactive router, it refuses to connect any traces to/from these pads because their clearance is tighter than the design rule allows.
If I decrease the allowed clearance to 9mil, it routes, but then it’ll pack the traces at 9mil, and it’s nearly impossible to manually correct to 12mil for the rest of the trace, because it will pack more traces between vias than I have room for at 12 mil spacing.
This seems like it would be a common thing for anyone routing memory chips, or other relatively wide and high-ish speed parallel buses to have to deal with. Is there any efficient way of doing this? If it was only a few traces, I would just fix them up manually, but that gets really impractical when it’s a crowded board and I have tons of traces to impedance control and length match.