Trace went too close to pad, yet passes DRC

This, amazingly, passes DRC. Note trace TxD inside two corners of the clearance area for pin 5. Also, the corner of pin 4 is similarly clipped by a trace. That’s just wrong. This exposes bare copper. See the 3D view:

What’s going on here? I’ve never seen this happen before. Autorouting placed those traces. They pass DRC. KiCAD is happy. But wrongly so.

Footprint: TO_SOT_Packages_SMD:SOT-353_SC-70-5
All design files:

KiCAD version info:

Application: kicad
Version: 4.0.6-e0-6349~53~ubuntu16.04.1 release build
wxWidgets: Version 3.0.2 (debug,wchar_t,compiler with C++ ABI 1009,GCC 5.4.0,wx containers,compatible with 2.8)
Platform: Linux 4.4.0-81-generic x86_64, 64 bit, Little endian, wxGTK
Boost version: 1.58.0
Curl version: libcurl/7.47.0 OpenSSL/1.0.2g zlib/1.2.8 libidn/1.32 librtmp/2.3

Those are pretty large solder mask clearances.

But on your subject of copper/pad clearances I have no idea without sitting in front of your machine.
The nightlies use radiuses to determine clearances nowadays, but yours is a 4.0.6 stable, so this shouldn’t be of concern.

You can download the whole project from Github and reproduce the problem; see previous message.

It looks like this happens whenever a diagonal trace comes close to a pad. Here’s an ordinary resistor with this problem.

I didn’t see this until I turned off 3D models and the silkscreen layer.

Now this is something I had fabbed, and here’s that part of a real board.

The solder mask opening is slightly smaller than the layout program or the 3D view indicates. On the real board, there’s no exposed copper corner.

I have a solder mask clearance of 0.2mm set. KiCAD’s default is 0, but the fab doesn’t like that. It looks big because that’s a small part.

As I look at the board layout zoomed way in, I find more of these. Not sure if this is ever a real problem. I’ve done boards in KiCAD before, but this is my first adventure with 0.5mm pin spacing.

As you can see there is jitter between the actual copper pad placement and the soldermask… if they had used ‘0’ there, the soldermask would sit OVER copper pads in places.
That’s why it’s usually a positive value.
The smaller, the better the fab needs to be (=less jitter) for your pads to be fully exposed.

As for the track/pad clearance at the corners… have you tested to do a track manually and how it behaves then?
Does it let you get as close as the autorouter?

Maybe DRC checks for those violations based on radius and the autorouter does it’s work based on radiuses also, but the manual placement works on the simpler edgy case (for the stables, the nightlies can do radius as I said) and your confusion stems from that?

I had always thought the DRC checked for clearance violations based on radiuses, not just in KiCAD but also in other layout programs I have used. I don’t know where I got the idea but the observations here in this thread seem to confirm it. That square-cornered box is a very helpful guide, and you’ll never go wrong while keeping traces outside the box, but the acceptable routing area is a little more generous than shown by the box.


As I said, nightlies do show rounded clearance zones for corners now, so I can’t be of much further help here.

OK, going back to the old files from a previous board, also all autorouted. All files in this post are from the same set from a completed job.

Gerber files. OK.
Note space between solder mask opening (blue) and front copper (grey) at upper right corner of pad. No rounded corners here, but there’s clearance.

3D view. OK.

2D view. OK
Corner of red outline of clearance limit clips the trace above pin 2, but would be fine if rounded corner.

Actual board. OK

So there was no problem with the design rules used on the old board. Looks like narrowing some things for narrower pads elsewhere on the board caused trouble. More later.

I think I’ve figured this out. On the old board, I had a minimum trace clearance of 0.27mm, and a solder mask clearance of 0.20 mm. That works.

On the new board, I have a minimum trace clearance of 0.20 mm, and a solder mask clearance of 0.20mm. That will expose some bare copper in those corner-cut situations.

So the solder mask clearance must be smaller than the trace clearance. By how much? At a corner, we have a triangle, with TC the length of the hypotenuse and TC the length of the other two sides. so

TC/SMC  = sqrt(2) = 1.41.
SMC/TC = 1/sqrt(2) = 0.707

So if I have a trace clearance of 0.2mm, the solder mask clearance must be no larger than 0.154mm.

Seeed studio has a minimum fab requirement of 0.10mm solder mask clearance. If I use 0.15 as a design rule, the 3D view looks clean, with no tiny bits of exposed copper.

Rule: Solder mask clearance cannot exceed 0.707 × trace clearance.

KiCAD should probably check that.

Which autorouter are we talking about?

Routed with FreeRoute, the one that more or less comes with KiCAD.

That doesn’t take the soldermask registration variation into account, which depends on the fab and is not expressed as a percentage but as an absolute value.

Their blog talks about 3 mil minimum clearance, so I’d say that they are able to place it +/- 3 mil, while still being able to guarantee that your pads are 100% free.
Economic fabs (esp. Chinese) will give you 4 mil (0.1 mm), while the better ones are able to guarantee 2 mil (0.05 mm).

0.707 x 0.2 mm is ~0.142 mm, not 0.154 mm
If you then take the 3 mil (=0.077 mm) registration tolerance into account you wind up at a soldermask clearance of 0.065 mm that you should not exceed, if you want to make 100% sure that no copper track is exposed.

I use 0.05 mm soldermask clearance, 0.1 mm soldermask minimum width and 0.2 mm track clearance for these kind of boards.


Of course. That constraint applies in the other direction, too. The registration tolerance of your fab limits the track width.