Trace Spacing Issue

Hi All, This is my first post so hope to get the etiquette correct.

I have been using design spark for 3 years now but wanted a few things which it didn’t offer.

So decided to put the effort in and learn kicad which i like a lot.

But i have an issue. (I ran the DRC with no errors).

I have finished my boards and have plotted the gerbers and drills. Sent the zip to Jlcpcb and i’m getting minimum trace spacing of 3.62mils all the design rules track spacings have been set to oshpark regs 6 mils clearance and track width and so on, the copper pour areas have been set to 10 clearance and minimum width 6 there are 3 within a ground pour which have “Zone priority level” set to 1 above the main ground plane which is set to zero.
If i don’t pour the copper before sending then i get a clearance of 5.91 which still i don’t understand it should be no less than 6. When i send with copper poured i get a clearance of 3.62.

I have been deleting different parts of the board and sending just to try and pinpoint the issue.
All the evidence points to the copper pours.

Any help would be greatly appreciated

I’m using a nightly build which is working very well no more crashes which i was getting on the release 5.0.1. to the point where it was unusable .

I have added the build version below.

Application: kicad
Version: (6.0.0-rc1-dev-1267-gff668968f), release build
wxWidgets 3.0.4
libcurl/7.61.1 OpenSSL/1.1.1 (WinSSL) zlib/1.2.11 brotli/1.0.6 libidn2/2.0.5 libpsl/0.20.2 (+libidn2/2.0.5) nghttp2/1.34.0
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
Boost: 1.68.0
OpenCASCADE Community Edition: 6.9.1
Curl: 7.61.1
Compiler: GCC 8.2.0 with C++ ABI 1013

Build settings:



I’m sorry but this is difficult to understand, at least for me.

  • Sent the zip to Jlcpcb

OK, but didn’t you check the gerbers first?

  • and i’m getting minimum trace spacing of 3.62mils

What do you mean, “getting”? Do you mean that there are traces which are 3.62mils apart even though the clearance value is set to something more?

  • If i don’t pour the copper before sending

You always have to fill the zones and check the gerbers before sending anything to anywhere.

  • then i get a clearance of 5.91 which still i don’t understand it should be no less than 6.

Again, where and how do you “get” that clearance? Are some two things 5.91mils apart? What?

  • When i send with copper poured i get a clearance of 3.62.

And again, where’s that clearance?

It would be easier if you gave some screenshots.

Hi sorry for confusion,

I always checked gerbers first.

I have been over the gerbers many times and cannot see any issues with spacings at all.

I sent the to the fab many times with different options set and also with the copper pour areas on and off to try and see where the fab was having issues. I was never going to send the board to manufacture with copper areas off it was just to see where the fab analysis was going wrong.

As far as i can see Kicad is doing the clearances fine its just that i may have missed something obvious because i’m new to the software.


Hi Malc,

It sounds like JlcPCB offers a DFM (“design for manufacturability”) check on submitted files before the order is accepted for fabrication. In my opinion, that’s commendable because it reduces misunderstandings between the designer and the board fabricator. (And this thread is an example!)

Did JlcPCB provide a more descriptive error message, perhaps identifying the component(s) or geometric location(s) where the spacing is inadequate?

Some DRC and DFM algorithms take a very conservative approach, measuring clearances from square-cornered boundary boxes rather than geometrically correct radius corners. (I seem to recall that even KiCAD suffered from this a few releases ago, when the on-the-fly dynamic DRC calculated clearances using a different algorithm than the static DRC check.) If that is the case, the folks at JlcPCB are aware of it and may accept your design for fabrication if you solemnly swear and affirm that you will accept the consequences.

I notice that some of your copper pours (a.k.a. “fill zones”) are a little ragged in certain locations. Try experimenting with the zone parameters - especially priority, corner smoothing, and arc segments - to make the filled areas a little smoother. Have you specified “Polygon” fill mode rather than “Segment”?



Hi Dale,

Thanks for the really great answer, i think i should have been a lot clearer in my question at the start, but yes you are correct and i was using their “DFM” as a checker (not sure it was designed for that).
I think i have found my issue, in Design Spark you are able to set the board to track & board to shape clearances, this takes care of the edge of the copper being set at the correct distance. I took the same approach with placing the copper pours which tripped me up. I have moved the copper pour layers 15mils in side the edge cuts and i am able to pass their test, although still unsure why the distances are different on the “DFM”.

I have played with the “copper zone properties” but cant seem to get the fills any smoother, since using the nightly build things have changed and i cant seem to find the options you mentioned.

These are the options i have now.


If the issues were copper to edge clearances, you can use another trick in KiCad making your edge_cuts lines thicker. This is because the defined board edge is the center-line of the edge_cuts line. But KiCad’s DRC treats the edge_cuts lines as copper for clearances. Thus DRC (and copper pours) will calculate the copper spacing to the edge of the edge_cuts lines. So DRC passing copper will be the defined clearance plus half the width of the edge_cuts lines from the actual board edge.
(There may be some edge cases that I’m unaware of that make this technique invalid.)


Thankyou for the tip, will give that a go. I’m sure as i get more used to the software life will get easier :slight_smile:


If you are learning KiCad, version 6 is a nightly build version that will be ready as v5.1 not before February 2019. Downgrade to 5.0.1 is safer.

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Hi Pedro,

I would have happily carried on using the stable release, but it became so unstable that it would crash every few seconds, so i really didn’t have much choice but to use the nightly build. I understand that it may have issues which is why i’m checking my work constantly.

But thanks for the heads up :slight_smile:


The “Zone Properties” dialog has obviously been reworked. Previously it looked like this:

The only things that may help you are “Priority” (set the “GND” or other large zones to fill last) and possibly increasing the fillet radius.

The trick for dealing with board-edge setback requirements is to make the Edge.Cuts lines wide. The fill algorithm treats lines on the Edge.Cuts layer as if they were traces, keeping the copper away from the line by the zone’s “Clearance” parameter. So if your zone’s Clearance is, say, 10 mils and you need 50 mils of setback from the edge, then make the Edge.Cut lines 80 mils wide. Half of that width (40 mils) will lay on the board, and the fill algorithm will add another 10 mils of clearance to the line, for a total of 50 mils between the copper pour and the actual board edge.

If you don’t like to see those wide lines on the Edge Cuts layer, select all of them and reduce the line width to 4 mils or 6.2832 mils or whatever width pleases your aesthetics AFTER you fill the zones. REMEMBER . . . the KiCAD DRC algorithm will automagically refill the zones, so don’t reduce the line widths before running the last DRC.

Of course, this trick only works if your board fabricator mills the board outline to the center of the Edge.Cuts lines. If your fabricator is a quarter century behind the times and mills to the inside or outside of the Edge.Cuts line you’re not totally screwed. Use the same thought process to develop a procedure (widen the lines, fill the zones, narrow the lines) that is compatible with the milling process - the details of the arithmetic will be different, and is left as an exercise for the student.

When laying out a board, I seldom set my global DRC constraints to the limits of the board fabricator’s capability. If he says that 6 mils is the minimum feature size for a routine job, I’ll probably keep everything at least 8 mils, or 10 mils - and most of the features will be larger than that. Of course, some situations may absolutely require operating right at the limits of what he can produce but I don’t believe there is much to be gained from doing the whole board, or every board, at his limits. It certainly eliminates situations where he looks at his micrometer from a different angle than I look at mine.


Hi Dale, i tried all of the above, it still produces the same.

I tried Pedro’s idea of increasing the line sizes and it works, i don’t mind the the thick line it doesn’t bother me.

Also like yourself i don’t drive the DRC constraints to their minimums as that’s just asking for trouble.


I just received an email back from the fab JLCPCB.

Thanks for your e-mail , for your order Y1 , it’s under producing now , and the tracing width Min 0.15mm ,. Some times the analysis is not very exact .

And if there are problem for your file ,we will informed you .

So sorry for that .

seems that it is an issue with the DFM checker.

Anyway thanks for all the help.


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