Hello, good afternoon, my friend. I’m having problems with the screen printing blocked, the solder mask, the electrolytic capacitor, and the SOT-23 footprint.
Kicad 8.0.8
It is normal that if silkscreen will not print where it overlaps the solder mask (cleared area for soldering).
Can you post a screen shot of your issue?
I leave photos of the Kicad screen, maybe the SOT-23 solder mask is already blocked.
Doesn’t the SOT-23 clash with the electrolytic capacitor for space? In fact what is a big elctrolytic cap doing on this board?
You can’t expect new footprints to be identical to your old ones.
Just move the component text, or if that’s not possible because you want to duplicate the old board, create new footprints that match the old ones.
I have difficulty understanding the lower layout.
For example I see a large rectangular box labeled D5. But it seems to be a large axial (something) with two diodes and something else in it.
And the electrolytic capacitor and (SOT23?) are in the same PCB area.
Yeah that is my second point. But when I think of “clash” I think of a polka dotted shirt and striped trousers. This is more trying to put two components in the same volume. As a pcb layout it might be OK if only one of the two items will be placed. Can you “time-division-multiplex” the capacitor and the SOT23 so that only one is there at a moment; back-and-forth? 
Looks more like components are burried under other componets. The SOT-23 gets assembled, then the cap is set on top of it.
Or the connector (?) YF_LF… is set on top of the two diodes and the two resistors.
Doable if you are running out of space. Just ignore the errors if you wanted it that way.
Hello, it’s to affect the PCB, Gerber capacitor, and diode, along with the screen printing problem, silkscreen painting errors on the soldering pad. error DRC soldering and silkscreen.
YF LF is a common original factory unknown is a equipment device leister gun for canvas pcb project
I am not sure what else is going on, but it looks to me like that BAV99 at D3 together with C4 makes a charge pump.
It looks like you have lots of space available. Why not just place the BAV99 in the free space above J3? It will be much easier if you ever need to rework or probe the board.
Do you mean at about 7:30 o’clock relative to J3? I do not see much space between J3 and the upper edge of the PCB.
Thank you very much, I’m going to draw and route tracks. I finished my projects. I’ll let you know if something happens. Ready? Gerber PCB testing boards. What’s going on? Is there a C4 and D3 silkscreen error.
Sorry for not being clearer. When I specified “above” I meant relative to the orientation of the board taking the orientation of the silkscreen text into account ie. rotate the images 90 degrees clockwise.
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I’m not using KiCad since close to half year.
I don’t understand the problem.
As I remember when generating gerbers there is the option to mask silkscreen with mask layer so silkscreen is simply deleted from all mask openings so it will be not printed at pads. I’m not at PC with KiCad so can’t check it - did that option disappeared?
If you don’t use that option than you still have may be 70% chance that PCB manufacturer will mask out silkscreen.
Do your whole problem is that KiCad when you design PCB doesn’t show what will be the effect of you using or not using one option when you will be generating gerbers?
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Maybe the electrolytic is on the opposite side . . . it’s a reverse engineering job so to get proper answers about design intent we would need to ask the designer not the copier 