I believe that most chip makers actually buy in lead frames from third parties, so it is a bit odd to have two varieties to TO-252-5 unless the JEDEC standard allows both as suffix variations
specially to Kicad. If you decide to use a N-Channel Mosfet you have to decide between identical looking symbols what are:
Q_NMOS_DGS
Q_NMOS_DSG
Q_NMOS_GDS
Q_NMOS_GSD
Q_NMOS_SGD
further more for the 4 pin models with connected tab. Hopefully every designer knows by heart the TO220 of his IRF540 counts GDS. Otherwhile there is a wrong layout without any further warning on forward annotation or footprint assignments. Urgent time to improve this using the database and shrink the symbol library to a fraction.
You missed:
Q_NMOS_SDG
Drain is normally substrate and sits on the tab, except for some RF devices, making GDS by far the most common variant
Designs use only custom footprints; that may be created from a KiCad library footprint. Each footprint has the basic size/shape of the physical part created on the F.Fab layer (shown in blue in the image.)
The KiCad, or other trusted, 3D model is then checked against the custom footprint.
In the image, both C1 and U1 line up as expected; both on the board layout and 3d viewer.
Or how about a Q_Dual_NMOS_PMOS_S1G1S2G2D2D2D1D1 ?
FETs are really a pain, because there is no standard at all regarding package or pin assignments. But having a proper symbol (rather than a plain box) really helps the legibility of the schematic a lot.
So if you want a nice schematic, you find yourself continuously adapting symbols and footprints each time you use a new FET.
I can’t quite imagine what it might be, but it would be amazing to have a solution to this… perhaps something based on the pin-names used in symbol and footprint, like an auto-mapping for pins named “D, G and S”? Then we could reduce it to one symbol for FETs, with the differences in the footprints, where they belong…
There is a solution to this, and it has already been mentioned at least 3 times in this thread, and that is setting up a database with parts that are interesting for you.
What would this achieve?
Having a handful of generic schematic symbols is not a problem in any way. It’s not difficult to select, does not take up much disk space (compared to 3D models), and a handful of symbols is also not going to confuse users. Why would moving the “perceived problem” from a handful of schematic symbols to some extra layer of indirection by adding pin mapping be an advantage?
In KiCad, “pin numbers” are actually 4 character alpha numeric strings (meant to enable “chessboard mapping” for BGA’s and other high pin count parts. But using “G”, “D”, and “S” for pin names would just move the problem to the footprints. Now you need footprints with those pin “numbers”, and you duplicate that for BJT’s, diodes and other parts.
That’s not an interesting solution for non-companies.
While I understand and have no issue with the database use-case for some company, where multi-user use cases are important, and there may even be persons repsonsible for keeping this database up-to-date, I don’t think its a good fit for me (or most other individual users).
As a non-professional and solo user, I’m not interested in configuring and filling a database in order to use my EDA tool. I’m perfectly happy using KiCad’s built-in symbol and footprint managers, and the better these are out of the box, the less work I have to do myself.
That’s not the problem…
I disagree. It’s very confusing. Take a symbol like Q_NMOS_GDS and any given FET footprint, and you won’t be able to say if the pins match the footprint. You’ll have to check each time. As you work with a schematic, changing components due to design changes or parts availability, you have to recheck each time. Often you have to adjust footprints or create variants as the footprint’s PIN numbers don’t match the symbol’s. This process is annoying and error prone.
Agreed.
From my point of view, this would be a significant improvement. Obviously it can’t work for all parts, or BGAs in general, or abstract use-cases like this, but that’s not the case here.
For FETs, and a wide array of other parts, you can assign standardised names to the pins - D,G,S for FETs, B,C,E for BJTs, + and - for Diodes and polarised capacitors, IN+, IN-, OUT for OpAmps and probably quite a few more.
The advantage is clear - one schematic symbol works with a variety of different footprints, regardless of different vendor’s pin numbering conventions.
On the other hand, I don’t see any big advantages of the current system (other than being the status quo, of course), since I don’t think anyone actually benefits from assuming by convention, for example, that pin 1 of a LED is the cathode, only to find out later it isn’t.
And even if they catch the error beforehand, they don’t really benefit from having to edit the footprint or symbol to make things fit the numbering convention.
Thanks for pointing that out, I should have known from the BGA parts… so actually this means KiCad could already do what I envision? And I all I have to do is create some symbols that work in this way? That would be great 
Drawing symbols is a lot easier than drawing footprints and minor errors are less relevant. I understand your reasoning and there would be advantages doing it your way, but I like only having to draw/edit e.g. a SOT-23 footprint once and not having to create tons of variants with different pin assignments.
FWIW, @runger, I am in complete agreement with you.
I think that FETs on the schematic should have their pins labeled GSD, and then I can pick the correct footprint for the particular device I am using. Having the pins labeled 123 just means there is another level of indirection that needs to be navigated.
Of course, that’s the way my old system worked, so maybe I’m just biased.
That leads to a variety of TO-220 etc footprints with all permutations.
There’s no getting away from something having a big variety.
Either it’s a zillion parts and all their packages, or footprints with every possible pin permutation.
I think the latter is more manageable.
Now apply the same logic to the 14 and 16 pin DIL packages for 74LSxx and CD4xxx series.
You end up with the Eagle linked footprint and symbol world
Yes if you are doing power, you will not lose a lot of component choices by dismissing all that are not GDS.
I counted 1.309 zillion.
For a TO-220 that would be
- 6 for FET’s.
- 6 for BJT’s.
- Several for single and dual diode’s.
- A separate one for an LM317, and who knows what other IC’s…
- The good old 1 2 3 just to be sure?
Maybe 20 in total?
And KiCad now has three TO220 footprints, A vertical, tab up and tab down variant, so that would become 60.
How is that an improvement?
I like and prefer the simplicity of footprints being independent and just having pin numbers, and that is how it should be for generic parts. KiCad does have enough flexibility to give the pins short names, but then you’ll have to maintain your own libraries.
1 Like
This all is an important question of workflow for library maintenance and circuit design.
For library maintenance, the wish is to maintain only one N-channel fet graphical symbol. Maybe there are several alternative styles maintained like resistor as european box or american zigzag symbol but not for every value. Footprints remain like they are as there is not a seperate footprint for every resistor value.
The task of the database is to connect the entries by links. The result is a third kind of library what contains only ASCII information for manufacturer and/or company order numbers, swaping rules and pin assignements. There could be features imaginable to switch a schematic style from european DIN style to american ANSI style or to the @mgyger Elektuur Style with one click by switching the database links.
On the other hand, there is the design workflow. Extreme example are connectors. If you introduce any connector in your design, you wont spend any time to think about the thickness of gold plating. Therefore the schematic editor needs a place symbol command like it is for the moment. Designer may place any connector symbol and is able to go on with more important decisions for that stage of developement. Later he decides to connect a footprint what needs to narrow the selection of connectors much more. Unfortunately, the resulting BOM cannot be passed to the purchaser, as he does not know what to purchase for this design. Here, the database comes into design. Instead of assign any footprint, we assign a database entry what can be purchased and the footprint is assigned automatically. Together with padstack libraries, this not only allows to switch the schematic style but also the pcb style from „hand soldered“ to „wave“ or „reflow“ footprint styles with the very same footprint.
After iterating several future Kicad versions, the schematic editor should offer the possibility to place a symbol like it is now and alternatively to place a symbol from database including correct footprint and BOM entry. The advantages of the first command is to allow the designer to go on with major important design questions. The advantages of the second command is to have a 100% specified design for manufacturing. This minor important questions may be solved by the designer in a later design stage or by any other helping person what may be more familiar with manufacturing and company stock items as the designer itself. For the moment Kicad cannot do this design workflows but developers like @craftyjon struggle to come into the correct track using the V7 database. There are many related posts here in the forum and gitlab issues and epics but I am still not sure, if all of the developers see the possible goals and benefits for the future Kicad design workflows.
@paulvdh wrote: Now you need footprints with those pin “numbers”, and you duplicate that for BJT’s, diodes and other parts.
Pin mapping is a ASCII task for the database to keep other libraries simple.
1 Like
It’s free, but you have to register.
https://www.jedec.org/document_search?search_api_views_fulltext=to-252
There are five variants (labelled AA-AE) The five pin AD Variant (four leads an tab) uses a 45 mil center to center lead spacing.
Rich
The TO252-5 standard is easy to find. Just ask the internet. Well, not the military version.
In this case, it says 1.27mm.
But the datasheets you refer to (ON Semi etc.) have a statement included:
F EXCEPTION TO-252 STANDARD
This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.