To hide GND net

Trying to hide GND net I manually remowed that net from net file and reread the net file.
But the GND net didn’t deasapeared (KiCad 4.0.7).

Begining to write this I found in “Your topic is similar to…” that pouring GND I can hide it. It works, but I also have to hide F.Cu to see it close to what I need. It is acceptable but I wonder…

Why after rereading the net file the GND net left. I checked many times if I really deleted the GND net form net file and if I read the right file. Chcking “Delete” for “Unconnected paths” And “Delete” for “Net names of not connected pads” didn’t helped. Checking “Delete” for “Additional footprints” delete all my footprints - I don’t understand - they were not added by me manually - they are in netlist.
I remember that about half year ago I have done the same experiments and it worked, but I’m not sure - may be I deleted GND form net file before first loading it.

Do from that description you can find what I’m doing wrong? It looks like my net file is not loaded or the nets are not deleted before loading the new net file.

First, I do not understand why you want to delete the GND net.
I assume you are aware that your circuit won’t work if you do not connect the GND pins properly.

Have you thought about (temporarily) adding more copper layers to your board and connect GND to a copper pour on the inner layers? I almost added that workaround to the other thread, but the OP there was already happy with the solution given.

Completely hiding GND seems like something usefull on first sight, but if you do not spend enough time/effort on your ground plane and try to connect GND only at the very end you might put yourself into a position with more trouble than the problem you wanted to save yourself from in the first place.
Good GND planes are an important feature of a PCB design.

Under very old Protel 3 I am still using (in free time I am trying to move to KiCad) my first steps after importing a net to PCB are always:

  • change the GND connection lines to be blue,
  • change teh VCC connection lines to be red,
  • hide the GND connections.

I am designing 2 layer PCBs with whole bottom destined for GND so GND can be connected at any place.
My first task is to place elements that way to be able to make all connections (except GND) on top.
To do that I need to see all connections except GND during placement.
If I will use 4 layer PCB I will probably need to hide GND and VCC during placement.

As I can’t hide GND connections in KiCad I supposed to delete it for time of placement.

What I don’t uderstand is why importing net file from which I deleted the GND net don’t deleted the GND net on PCB.
Report says (translating from Polish):
Info: Reading net list…
Info: Use footnote names while connecting components to footprints.

The second one is Info, not Error. I don’t unerstand what it is about. May be understanding it will tell what is going on.

If Polish, then you can understand this probably better than I can:

I found the source of my problem.

It is one of many doc files which in pdf format I have printed an year ago and read all marking with yellow marker everything what is important. I don’t know why you link it.

The source of problem is the text editor I used. I have never met such problem before.
I used Windows Notepad (not sure of English name) which is installed automatically together with Windows. I was sure that after text edition I have text file so I didn’t expected problems here and looking for problem source in KiCad.

May be some programmers can understand it, me not.
When I copy my net file and then open the copy for edition and then before the first ‘(’ I insert the space and delete that space and then save the file I got the file which looks be identical but is not.
Under Windows I dont see the exact size of the file (I only see 22KB).
I have compared them using WinMerge and it says: Both files are identical.
Under Windows 7 I have no tool (or may be have but don’t know) to see file byte by byte - I just not needed one before.
I’ve copied both files to my old Windows XP computer. There I at once noticed the difference betwean these two “Identical” files. After my edition the file is 3 bytes longer.
Looking inside my file after edition starts with: EF,BB,BF,28…
The original file containts: 28,…
And the rest is identical.

If I delete GND net with Notepad++ everything works as expected.
What is surprising for me is that even under Notepad++ if I open the file with this EF,BB,BF at the beginning and switch to show all invisible characters I see nothing before first ‘(’.

To show the need in practice:
It is the simple PCB I’ve decided to try KiCad first time.
After my initial placement.

On left without GND net on right with GND.
This one track is to make connection line to point where I plan it and not to the nearest point.
On left you easily see - all can be connected on top.
On right it is very hard to determine if with that placement you can connect everything assuming whole bottom is GND.
I don’t know how long it would took me to find the right placement if I had all the time to discower which line is importanat and which not. It is why I had to find how to hide GND even looking into hidden bytes in theoretically text file :slight_smile:
If I could have VCC red (like I’m used to) it would also help as I typically use wider tracks for VCC and during placement I am trying to avoid for example the need to pass with main VCC lines under 0603. This whole device will consume about 5mA so here it is not the case.

Now next step in front of mine - to discover how design rules are set in KiCad and how to use them, but I have to left it for a while (other tasks cry “do me at once”).

You can do what you want of course, but in my opinion simply connecting all GND pins to a single GND pour is not a good idea. For a good PCB design (Especially with higher current parts and Noisy/Quit parts) it is important to keep an eye on how the currents go through the ground plain.

For example, take a simple digital ic (uC, whatever) with decoupling capacitors.
If you connect both the IC and the decoupling capacitors to the ground plain, then all the noise the uC generates is injected into the GND plane. If you however put the decoupling caps close the uC and only connect them to the uC pins, and then connect that combination to the GND plane, the decoupling caps filter the high frequency noise of the uC and the GND plane only sees lower frequency current variations.
In a mixed signal design such details can be important.

In your example the difference of hiding the GND net is also very minimal. It’s like those pictures where you have to search for the 10 differences. But in the Right picture It seems that you have tried to keep GND pins of different components together. In my workflow I want to see such details. I do not want to hide them.

1 Like

I don’t have high currents (over 300mA) in my designs. Digital currents consists of many components. The
higher frequency of component the more it likes to travel back to source not the shortest way (in GND plane) but just under the signal line with that current. Having single GND assures all high freauency current loops has minimal area. Emission and sensitivity to noise is proportional to that area. The controllers I use (AtXmega serie) has VCC and GND pins in pairs on all 4 sides so the inner wires are close to each other. The current consumed by VCC goes back by nearest GND pin (of cource at each pair I have 100n). So these currents are not seriously inserted into my GND. I am speaking here only about high frequency components.

This is not discussion for KiCad forum but rather for any EMC forum. As in many subjects there are two schools: 1. Connect analog and digital ground in one point. 2. Have one solid GND. Try to design the digital scope with 4 inputs according to 1 (you need common GND for all inputs).
I agree with school 2. But that doesn’t mean that you need not to think which elements are where. Betwean analog and digital part you should have about 2 cm distance (GND continuous). The 99% of high frequency currents will stay in their part.

I remember Keith Armstrong articles serie on PCB design I read more than 10 years ago - hi suggests school 2. I like, specially his TidBits (one of them (don’t ask me which - don’t remember, long time ago) was done on suggested by me subject).

You assume that:

  • only VCC/GND uC pins are the noise source,
  • uC output lines don’t carry high frequencies.
    But the outputs do carry high f (even if they switch not so often - not only f but dV/dt is even more important). If things are done as you suggest the comeing back current from any load driven by uC output can have a problem to go back along the signal line (only high f components are in our interest) and they have to create bigger area of current loop (think also of wires connecting uC structure to his case pins) - which is not good. And uC has many outputs. The one solid GND is, in my opinion, the best solution in majority of cases (only majority).

Seriously? That is such a trivial board and the net names are visible so it is clear which nets are GND. When you get to more complex boards hiding the GND net doesn’t even make a difference.

You can! Use Protel. :wink: Kicad doesn’t work that way so get used to it.

Not yet. It is planned for some future version. One bug report that requests it is marked as needed for version 6:

Yes it is trivial, and Yes - seriously. When parts are placed it is easy to check that among each crossed lines one is GND so no problem, but when moving/rotating parts to unknot the connection the extra lines perfectly disturb me.

If you mean so comlex to use 4 layers then agree - there is no need to make them routable on one layer.
Buf if only 2 layers and with assumption bottom is only GND then hiding GND makes (al least for me) very big difference.

An year ago I decided to try KiCad. I was fascinated with the demos how routing works. The Protel I have is very old (1997) and don’t wont to run o Windows 7. I can install virtual XP on Win 7 but I decided to not do that and have this way the next reason to try kiCad.
Until now I suppose placement is a little worse (for me - hiding GND is a little more complicated) under KiCad and I didn’t start routing yet. I’m sure it would be much better then under my Protel, but to be experienced user certainly I will need a time.
I do only a few PCBs per year so learning KiCad can be seen as a kind of hobby (I would spend less time using Protel I know well), but I’d like to try something new.

Are you sure KiCad will never have a possibility to select the color for each net connections (with invisible among them)?

Nice that you quote “me” but ignore what i wrote :wink: (That statement was part of my post. But it was a quote from @1.21Gigawatts. So you should have quoted the original.)

You’ve somehow misquoted @Rene_Poschl as it was I who said that. This feature has been requested and has been given a target release of 6.0rc1. Since 5.0 isn’t even out yet 6.0 is likely to be at least a year away if not 2 or more.

But seriously, you’ve spent more time on this thread then it would take to route that board. In your side by side images I can count 5 net lines that disappear, there may be a few other short ones I don’t see, but you call that “a very big difference”?

Sorry. I was writeing rather long time (I read/write very slowly checking some words from time to time in dictionary). I remembered what sentence I plan to quote and when come to it looked for that sentence and quoted without notising that there are a new post there. I am also not used to look to the right part of screen so I didn’t noticed what I have done. I have read what you have written after I send my post. Then I sow that my last sentence has no full sense, but I still didn’t noticed that I quoted from your post.
Once more Sorry. I must used to look to the right.

Yes, you are right (in “it would take”). But if someone seys something in generated by me thread I feel being forced (not exactly what I woul’d like to say) to unswer.

But even if for others “it would take” little time I will certainly spend much more time on it because I don’t wont only to have this PCB done. I wont to understand all possibilities of design rule settings. And they are only little mentioned in doccumentation files, and I remember that I rather didn’t understood what was said about them. I just know nothing about it and have 0 experience in KiCad routing.

I am speaking not about that simple PCB. I showed it as an example (the only one I have till now). My typical task is to unknot the lines goying from 64 pin uC. I know that for people using BGA it is small, but I am using one layer + GND. For me it is really important to see only lines that I have to do something with them and no others. Even if I had GND lines blue they disturbed me. May be for others it is not a big problem but for me it is.

This topic was automatically closed 30 days after the last reply. New replies are no longer allowed.