Through hole as a net-tie in V7?

I am having a couple of problems with my 4 terminal current sense resistors in V7, trying to avoid errors and warnings.
Is it possible for a through hole to connect two nets on different layers, using the hole as the net-tie?
Using the pads as the net-tie causes errors as below

That error is rather minor and related to the solder mask. Can you show us a screenshot of the soldermask layers active?

Maybe you have to adjust the soldermask setting of the pads or draw a custom soldermask area yourself.

It was 6.99
V6 introduced settable net-tie pad groups in footprints that allowed me to make clean boards with zero errors and warnings. This seems to be a regression in V7, that the net-tie pad goups are ignored. I realise that this is actually a minor error.

The same error happens if I use all SMD pads and connect with a via

I attach the F.Mask layer

Not really, V7 introduced an additional DRC warning if different nets are connected through the same mask layer hole. So while this might be a bug, maybe the developers didn’t see this because they assumed net ties would be always covered by solder mask and you wouldn’t create such a pad and net-tie hybrid object. Maybe this new warning also needs disabling in case of allowed net-tie connections, but it’s not really a regression.

I’d create an issue on the bug tracker and ignore the warning for now.

I will try to test exactly what combinations trigger this. My feeling is that in a footprint where pads are declared as allowed to touch, that the lack of mask error should be silenced. This is worth raising as an issue

Net tie pad groups were introduced in 6.99 / V7


Further experiments show that the mask test ignores pad groups and always fails DRC in PCB editor.
It can be fixed by checking the “Allow bridged solder mask apertures box”

I would call this a minor bug with a work around

The footprint
4_term_res.kicad_mod (1.7 KB)


That was quick

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