Thermal Vias under LDO regulator

I am new to using Kicad 8.0, so please excuse any incorrect assumptions.

I have a LDO regulator that does not have adequate thermal pads to cool it. ROHM BD00D0AWFPCT-ND
My board is approximately 20mm by 20mm, The device is on the front of the board, with about 1.8 watts worst case across the device (Vin = 15.25, Vout = 11.7, Iout = .525 amps.
The board is 4 layers, with the 2nd (GND) layer from the top configured as 2 oz copper, as is the front layer.
Currently I have 31 thermal vias (0.6mm with 0.3mm holes) to transfer the heat to the 2nd layer. I am trying to determine the best size and how to configure the thermal vias. I have read that the thermal pad should be covered in solder masking, but that doesn’t make much sense as it will increase the thermal resistance from the case to the thermal pad.
I have also heard that vias will allow the solder to wick away from the top pad, resulting in an inadequately soldered device. I think this may depend on the via hole size?

Is this the best via to use for thermal transfer?

Here is my front layer:
image

Here is the GND plane (2nd layer):
image

Also, does it cause a problem if the bottom side also has a plane - will the solder then wick through the vias?

Thank you for all of your help.

I hereby certify that I am not simply asking someone else to design a footprint for me.

This is an auto-generated message that is in place on the “footprints” section of the KiCad.info forum. If I remove it and ask for a footprint to be designed anyway, I understand that I will be subject to forum members telling me to go design my own footprint or referring me to a 3rd party footprint site.

Also, is there any reason to not create another thermal pad on the third layer of the pc board, isolated from the power traces?

Thanks for the advice.

My $0.02 suggestion would be to do a topside GND pour to make the Cu area around the thermal pad pin 3 be as large as possible. You can then do thermal stitching around the peripheral of the thermal pad that is just outside of the solder paste area. Thermal vias outside of the paste area wouldn’t be subject to solder paste wicking. While adding more thermal spreading area on all the other layers will help, improvements to that first thermal interface on the top layer will have more bang for the buck.

I also suggest you consider moving a few of the traces to another layer, again to make the thermal pad heat spreading area on the topside as large as you can.

You’ll probably still want several vias directly under the part, and if solder paste thieving is a big concern you can make multiple paste pads and place the vias where the solder paste isn’t.

I note the max Pd for that package is listed at 1.6W so you’re pushing it at 1.9W, You’ll want all the Cu area on the top side you can muster IMO. Maybe consider things like a different approach or things like reducing the dropout voltage. Hacks like two >1A silicon diodes in series with Vin would lower the dropout V by ~1V and move >500mW out of your LDO and into the dropping diodes.

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You should read the RHOM application information. Specifically:

RHOM Thermal design

Also important is the packaging of the PCB and what else is generating heat.

I thank both of you for your answers. I certainly did see the maximum power dissipation, but I believe that is for the device mounted on a board with no thermal pad. I may be reading this wrong - Page 7 of the datasheet lists that same 1.6 W value in figure 15 for a 70 x 70mm 2 layer board.

Figure 16 then shows the same size pcb with a thermal pad (example 1) and shows maximum power dissipation of 2.3 watts. Examples 2 has increased copper foil areas (70 x 70mm), increasing power dissiaption to 5.5 W, while example 3 goes to a 4 layer board, increasing power dissipation to 7.3 W.

Am I reading the datasheet wrong?

I suppose you’re reading it right. I didn’t dive that deep.

I have tried to search for that part at Mouser and at Rohm without success.
I looked through thread few times, but don’t see a link to datasheet.
My experience is that 1W dissipated in something like TO220 or DPAK makes it such hot that I can’t touch it. Fortunately I need not to work with high power.

Here is the datasheet.

https://www.rohm.com/products/power-management/linear-regulators/single-output-ldo-regulators/bd00d0awhfp-product

I had designed a board with the 1 amp version of this regulator, with thermal vias beside the top side pad, and the regulator shuts down due to heat, with about half the voltage across it.

My question was specifically about the proper way to configure the thermal pad and thermal vias under the device to provide the best heat-sinking.
Thanks for your advice.

Not sure if there is a KiCad question here . . . moved to Projects and set close timer appropriately.

I used whole name from your post (‘H’ in name was a source of problem).

Voltage limit, current limit and power limit are separate limits and you have to be under all of them.

Your board 2x2 cm = 4cm²
They specify 7x7 cm = 49cm² - may be even 10 times higher heat dissipation capability.

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