Thermal Via Connection to Ground Plane


I’m working on a board which involves a QFN-20 chip with thermal vias on the central pad. I set the thermal vias to be connected to the GND net, but when I fill the GND plane, very few of the thermal vias are actually connected, presumably due to design rules. Is there a way to get the ground plane to completely fill in this space?

Here’s an image of what I’m talking about, without the front layer pad.

Thanks for the help.

I can’t reproduce. Post a stripped down board file that has the problem.

Here’s a simple board which shows what I’m talking about. (21.5 KB)

There are some clearance issues with that IC footprint. The metal body of the USB connector wasn’t properly connected to GND as well.

To get the bottom copper to fill 100%, change the per footprint settings.

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That solved the issue, thanks for the help.