Thermal Management : What do you think?

Layout
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For lack of any good reason, I have a bunch of the MC33887 5Amp H bridge chips. The only annoyance with them is they don’t see a logic 1 if the input is less than 4.5v which means I have to level shift to use with a 3v processor, so maybe I’ll just use 5v processors. Like I don’t have a few of those laying around.

So I made a footprint for it:

579×512 7.3 KB

There are 50 .3mm vias under the pack to conduct heat to the 9 sq cm heatsink on the bottom. The bottom heat sink is actually bigger than described in the data sheet and there are more vias.

Is 3mm a good size for the vias?

I built it partly with the footprint editor and partly with a programming editor.

(module MC33887 (layer F.Cu) (tedit 57E92394)
(fp_text reference U* (at 0 9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MC33887 (at 0 -9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -6 7) (end -6 8) (layer F.SilkS) (width 0.15))
(fp_line (start -6 8) (end 6 8) (layer F.SilkS) (width 0.15))
(fp_line (start 6 8) (end 6 7) (layer F.SilkS) (width 0.15))
(fp_line (start -6 -7) (end -5 -8) (layer F.SilkS) (width 0.15))
(fp_line (start -5 -8) (end -1 -8) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -8) (end -1 -7) (layer F.SilkS) (width 0.15))
(fp_line (start -1 -7) (end 1 -7) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -7) (end 1 -8) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -8) (end 5 -8) (layer F.SilkS) (width 0.15))
(fp_line (start 5 -8) (end 6 -7) (layer F.SilkS) (width 0.15))
(fp_text user 1 (at -8 -7) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 5 smd rect (at -6 -0.635) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at -6 -1.905) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at -6 -3.175) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at -6 -4.445) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at -6 -5.715) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -6 0.635) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -6 1.905) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -6 3.175) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -6 4.445) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -6 5.715) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 16 smd rect (at 6 -0.635) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 17 smd rect (at 6 -1.905) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 18 smd rect (at 6 -3.175) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 19 smd rect (at 6 -4.445) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 20 smd rect (at 6 -5.715) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 15 smd rect (at 6 0.635) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 6 1.905) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 6 3.175) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 6 4.445) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 6 5.715) (size 2.5 1) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 0 0) (size 7.2 17.6) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 0 -12) (size 14 10) (layers F.Cu F.Paste F.Mask))
(pad 21 smd rect (at 0 12) (size 14 10) (layers F.Cu F.Paste F.Mask))
(pad 21 thru_hole circle (at -2.8 -6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 -6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 -6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 -6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 -6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 -4.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 -4.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 -4.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 -4.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 -4.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 -3.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 -3.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 -3.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 -3.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 -3.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 -1.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 -1.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 -1.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 -1.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 -1.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 -0.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 -0.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 -0.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 -0.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 -0.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 1) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 1) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 1) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 1) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 1) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 2.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 2.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 2.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 2.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 2.4) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 3.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 3.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 3.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 3.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 3.8) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 5.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 5.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 5.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 5.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 5.2) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -2.8 6.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at -1.4 6.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 2.8 6.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 1.4 6.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 thru_hole circle (at 0 6.6) (size 1.524 1.524) (drill 0.3) (layers *.Cu *.Mask F.SilkS))
(pad 21 smd rect (at 0 0) (size 30 30) (layers B.Cu B.Mask))
)

Next step is to put it on a board and print it to see if it comes anywhere close to fitting the chip.

Posted from a friend’s house where barefooted brats are allowed to use internet

2

You sound a lot more confident than you did a couple weeks ago. That’s progress!

My inclination is to keep the thermal pad(s) down around their minimum size in the actual footprints, and add heatsinking by using fill zones after I place the footprints on the board. That way I can exploit all of the available acreage for heatsinking, and at the same time allow other components to encroach on the heatsink area if necessary.

I also look for the fine-print footnotes on Data Sheets that say something like, “The thermal pad must be connected to pin number nn for proper operation.”. I make that connection in the footprint itself. This prevents my forgetfulness from leaving the connection off a final design. It also forces the thermal pad to have the same pin number as the pin it must connect to - avoiding the problem of having an “extra” pin to deal with on the schematic.

Dale

2 Likes
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Good thinking. Here, the thermal pad must be connected to ground.

I set the part on the paper and decided to widen the pads a mm to make positioning the part easier.

Posted from the Library where barefooted brats aren’t allowed to use the internet

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0.3mm holes in the vias are good. There is no point in putting far more vias than the manufacturer recommends; you may have a bigger heat pipe to the other side of the board but you have a smaller conductor on the other side as well and the limiting element is probably the solder between the chip and the heat pad. As for the size of the heat pad, manufacturers usually provide a chart showing pad size vs. core temperature. In these situations I size the pad so that I can attach a heatsink to it if I need to (I haven’t had to yet), but generally the pad isn’t much larger than the maximum the manufacturer recommends; the maximum in this case is somewhat arbitrary anyway and is a tradeoff between a useful heat pad and taking away too much board space.

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I deleted the bottom pad and just let the bottom copper groundplane connect to it free of thermal reliefs. Since I solder these with an electric frypan, I don’t need thermal reliefs anyhow. Oh, except on that 47uF through-hole capacitor.

Ok, new question: How to you put thermal reliefs for THAT pad and not THOSE?

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When you select “edit pad” you can specify its behavior within a fill zone: no connection, thermal relief, solid. The pad setting has precedence over the general zone settings.

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yeh, unless the PCB get bolted onto a heat-sink the middle vias doesn’t do much, the spreading resistance of the copper plane is so much bigger

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Found it. Thanks.

I reduced the number of thermal vias, Thermally relieved the th cap, laid it all out, routed it. Looks pretty good, I think.

511×512 23.9 KB

Oops. I think that LED footprint is going to put silk screen over the solder pads.

Posted from a friend’s house where barefooted brats are allowed to use the internet

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When ploting the gerbers you can select “subtract soldermask from silkscreen”.
This ensures that no silkscreen is outside of the solder mask. (Especially help full if you need to select do not tend vias.)

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Is there a way of DRC checking for silkscreen over pads?

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I don’t think there is. In my mind, this is a significant shortcoming in the DRC.

In years past I think the board vendors laid down the legend as specified in your files, though some of them would warn you about silkscreen on exposed copper and give you a chance to correct the files. These days, some board vendors will remove silkscreen that falls on pads (perhaps notifying you, and perhaps not). I’ve heard this practice used as a justification for omitting silkscreen checks from the DRC.

Dale

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Ending up with bad joints or missing Refs are both bad so DRC check would still be useful. If the output has the option to delete overlapping text, the only extra is some way of showing the location of the error

1 Like
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I just edited the footprints and took out the ends of the boxes around the LEDs.

Posted from the library where barefooted brats aren’t allowed to use the internet but I am anyhow

Last time I was here, the police came and arrested the guy at the next table for possession of stolen property. They had the owner’s cellphone telling them the computer was at the library and letting them watch the guy using it.

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With a little cleanup and a final DRC, it’s off to Elecfreaks. We’ll see what comes back. I got their automatic reply, but nothing else yet. They usually send an email when it’s about to be, or has been made.

1 Like