How do you assign multiple pin numbers to the same pin and have it look nice?
Case in point: OPA564 power opamp. I’ve just drawn the symbol, and it looks awful.
Check this (symbol editor shot):
Signals with multiple pins look terrible.
I tried making them non-visible, but that opens another can of worms.
Anyone have a suggestion for a good solution here? On large chips, consensus seems to be having a lot of power pins attached to the symbol, but for an opamp?
I’d draw a rectangle with individual pins connected externally. I’d also draw a graphic triangle in the rectangle to remind me it is an opamp.
I don’t like pin stacking.
I prefer to create a unit for the power pins. This then makes it easy to show the decoupling capacitors right next to the pins without cluttering up the opamp function circuit.
@davidsrb, I thought about that as well, but it’s not really universal. For example, the output of the OPA is two pins, and making an extra “output” box isn’t really an option.
In practice, there’s one thing to look out for: in the symbol editor, the last added pin is “on top”, so you should add the visible pin last. In the schematic it’s no issue.
KiCad has no Z-ordering, and changes like that are not guaranteed nor reliable. But there are at least 2 different ways to select / modify a pin unambiguously in the symbol editor.
A long click on the pin location.
Symbol Editor / Edit / Pin Table. You can right click on the top row with the labels to toggle visibility of columns (including the “visible” checkbox).
I don’t have an OPA564, so I loaded an OA569DWP into the symbol editor, and then added a new pin with pin name “asdf” and pin number 666, and placed it at the output. Is that what you think should trigger the “faulty” view?
In my opinion, if there are multiple pins at the same location, but only one visible pin, then the visible pin should always be rendered on top of the others. Also in: Schematic Editor / View / Show Hidden Pins is on.
I don’t know what triggers it, maybe it’s worth a bug report, maybe it’s already reported. My own preference is to go the other way. I normally unstack pins ans make them all visible. I want to see pin numbers in the schematic for debugging purposes.
I dunno what triggered it, my idea about the “last pin” was just a wild guess, sorry.
I agree that the visible pin should be on top, but it’s not on two signals. As you see, V+ is OK.
Bery odd.
Do you have a link to the library formats/documentation? I’m getting curious here…
There is: KiCad website / Contribute / Developers which brings you to:
And there is: KiCad Website / Libraries / Library Conventions which goes to:
I also did a short peek at gitlab. I do not see open issues for “hidden pins”, but there are a few open issues for “Z order”. (I did not read the topics).
I would draw the symbol with both pins visible, connecting both with a visible wire. I believe in “no surprises” for some future user of the board or even myself several years later. Having two output pins is unusual and someone could easily wonder what was going on
Thanks a lot.
I’ve worked it out by playing with the pin table.
The symbol editor places the pin with the highest number on top.
For OUT it’s a question of making p16 visible and p15 invisible, then the pin displays correctly (16>15).
For V-, the original pins are 1,10,11,13,14,20. If I make p20 visible and p1 invisible, display is correct. Doing the same with 10,11,13 or 14 makes no difference.
For V+ it’s correct, as the pins are 2,17,18,19, and 2 is higher than any other number starting with 1 (eg, 17,177,1777…).
This fits with the pin numbering in the .kicad_sym file; I checked that.
So the pins are displayed according to pin number, the “invisible” flag isn’t taken into account.
Whether this is a bug or a feature, I don’t know. I’ll leave that up to others to decide.
Can you explain then why pin 666 was not placed on top?
Best I know, there simply is no defined Z ordering, it can change with library management, symbol copying, planet alignment and moon phases.
I see the danger, and I’m also not quite sure how this is handled in a good way. To me, the schematic is about clarity and readability, and just because a chip manufacturer chooses to add pins to an amplifier (or whatever) should not impact that.
When using stacked pins, I’ll at least add a note to the pin that it’s multiple.
But a way of signalling that there are more pins behind a pin number like “3…” is unfortunately not possible at this time.
Perhaps because you added an Input on top of an Output?
I’ve no idea, it is chaotic. My hypothesis fits with what I have, but perhaps it’s really just random?
Coming back to the original question:
The “pin stacking” solution seems to fit my needs for readability and clarity in a schematic, but the information that it’s being used is missing.
I devised the following, which fits my needs:
The only thing that bothers me is the naming. “Pin stack” seems KiCAD centric and I’d like it to be universally understandable. How would you name it?
“multiple pins”
“multi-pin”
“additional pins”
“more pins”
etc.
“Stackable connectors” is quite common and you find references to it from multiple connector manufacturers. And there are plenty of other stacks too, From stack pointers to protocol stacks. Once you’ve used it a few times you’ll get used to it.
Just a question of communication (which a schematic is).
Will someone reading the schematic understand what “pin stack” is?
The connector connection (pun intended) is not really appropriate, nor are the other stacks you mention.
“Pin stacking” in a schematic was unknown to me until a few days ago, and I’m an old hand.
I think perhaps the issue with the name is that it’s describing a technique for hiding extra pins, rather than the fact that there are hidden pins. In other words, it’s sort of describing the symbol convention, which is nice when you want to know about the library/schematic style. But as the reader of the schematic what you really want to know is that all is not as it seems.
So perhaps something with the meaning of:
* and others
is more applicable.
My aversion to this technique (and I accept its benefits too) is simply because as the schematic reviewer, it looks like pins are missing. That is, it looks like a mistake has been made (wrong symbol). I don’t know (as the reviewer) whether the pins have been connected correctly. There’s no perfect solution, but being explicit rarely hurts. I like your asterisk technique - perhaps you could just change your text to: