Symbol pin label overwrites connection name

Schematic Library Symbols
1

I have a medium sized project with several hierarchical sheets used to instance sub systems.
I was noticed that there is an unexpected connection in the pcbs, and traced it back to the schematic where two instances of the same sheet have a falsely connected net. I’ve tried to remove as much as possible from these connections, and as far as I can tell the problem is that the LDR pin on the LT8722AV has connection name LDR in both sheets, and no amount of label / hierarchical label / global label is able to change this.

Even with no connections at all, hitting the ‘highlight same net’ button causes the unconnected pin on both instances to light up. This does not happen for any other pin on the same component, or any other components.

My current solution is just to try to ignore the fact that these nets have the same name, and ignore the DRC errors etc., but that’s not a great solution.

Many thanks

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2

Where does this symbol come from? Can you attach it? It’s not surprising for symbols and footprints from the Internet to have issues.

3

lt8722av-pbf.kicad_sym (7.3 KB)

The symbol was from mouser, I’ve modified it myself to rearrange the pin locations.

4

I’m unable to import it because I’m still running v7. However looking through the symbol with a text editor shows some anomalies.

GND should be type power_in, not power_out
LDR is assigned to both pin 8 and pin 9, and is of type power_in, probably should be input or passive

Did you run a check of the symbol in the symbol editor? From the icon or Inspect > Symbol Checker

1 Like
5

Thanks for the advice, I had a look through and a hidden pin was forcing the net labelling. I’ve made these be separate, visible pins and connected them explicitly, and now it all works.

I think I need read up a bit more about how symbols are constructed.

Many thanks!

6

I had a look at this symbol in KiCad V8 and it does look normal to me. The way pin 9 is made invisible is called “pin stacking” in KiCad, and it is common practice (but I do not like it myself).

Because I found your problem strange, and because it may be a possible bug I decided to go a bit further:

  1. Create a KiCad project for it.
  2. Putting the footprint into a library.
  3. Drawing some simple hierarchical sheets.
  4. Put the thing on a hierarchical sheet, connect some wires.
  5. Assign new footprint (I don’t have that ashley library, so used a simple 2.54mm pitch single row header).

After this, I was able to reproduce your problem, and it looks weird.
Pins 8 and 9 of the IC’s on the different sheets do connect to each other, even though there is only a local label on the hierarchical sheet. It also uses the net name “LDR”, while I used the local label “wire” in the schematic.

I also noticed pins 4 and 11 have the “VIN” label on the PCB. These are also stacked pins just as 8 & 9. and they also show ratsnest lines between the two different IC’s even though there is no connection in the schematic at all.

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Maybe the symbol is designed faulty, but even so, this should not lead to extra connections between hierarchical sheets.

I also have not seen the pin (net?) naming propagate to the PCB without labels before. If anyone knows: Is this some new function in KiCad, or is it a part of the bug?

If anyone else wants to have a look, I’ll add the project as I have it in it’s current state:

2024-08-01_asdf_resistor.zip (31.3 KB)

I also unchecked retiredfelines post as the “solution”. I do not consider this solved at all yet.

7

I confirm that unstacking the pins and making them visible removes the ratsnest lines between the different IC’s.

This symbol also uses more pin stacking:
Pin 5 is GND, stacked with 10, 21 and 22.
Pin stacking for GND is also not conforming the KLC. KLC specifies that stacked power pins must be set to the “passive” pin type to conform with the ERC rules.

Pin 6 is “SW” stacked with pin 7. And again, the stacked pin is of an output type, which will have ERC complain.

8

Perhaps I’ve skipped the info (and I’m not currently at my computer to check the symbol file), but this sounds a lot like the historical global power symbol issue: a hidden pin with type Power Output is always considered to have a global net name “under the hood”. I don’t know why the hidden pins with Power Input are doing the same thing though…
I had it backwards apparently, hidden Power Input pins are the global net names. S4.6 Hidden pins - Library Conventions | KiCad EDA

So the behavior seen here is “as-designed” to support older KiCad global power symbols. Unfortunately Mouser’s symbol creation script is just totally wrong here and the symbol needs some editing to be usable in KiCad.

9

Pin types for pins 8 & 9 were indeed set to Power Input. Changing both to Passive does indeed resolve the shorts between pins 8 & 9 between the two footprints.

This seems indeed to be the behavior. It also explains why the pin names appeared on the pads on the PCB. This is also new to me. I thought the symbol had to be defined as being a power symbol for power input pins to act as global labels.

So in the end, it’s not a bug and apparently we can not get rid of this behavior because of “historical reasons”. I have some mixed feelings about this. Disappointed there is no better way to fix it, but also somewhat relieved it is known behavior and not a bug. (Although, if it was a bug, it could be fixed more thoroughly).

So, to fix it for this symbol, set all hidden pins to the pin type “passive”. The quickest way to do this is is to open Symbol Editor / Edit / Pin Table. and then:

  1. Right click on the first row with labels, and show the Visible column.
  2. Click on the Visible column to sort the pins in that order.
  3. In the Electrical Type column set all the invisible pins to Passive.

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