while i’m happy that we get to hear from someone with so much experience in this field
and that KiCad’s interested you enough to tell us off so sternly
i would like to note that people are generally more likely to be convinced they’re wrong, if they believe you could be too
further, i think part of the confusion is that KiCad split into separate programs
and the schematic editor (as far as i, as a user, can tell) does not have the concept of a netlist, the netlist is the output of the schematic editor, not a concept within it
the netlist is the input to the PCB editor, and that is a mostly one-way relationship
however, i would say the prime intent of the schematic editor is to have a human readable schematic
if we just wanted a valid netlist, we would write it directly
Maybe what’s needed is an editor that turns the collection of wires into rats nests like with the layout editor. Then people can spend time turning the rats nest into neat orthogonal schematics. Arguments could erupt over manual schemating (is that a word?) vs auto-schemating.
No, not really. If all you care about is human-readability, you might as well go
old-school with pen and scales over a drafting table. See my initial statement:
In EDA, schematic capture is not about the schematic - it’s a visual tool for creating
a netlist, and the human readability, while nice, is incidental and unnecessary, because
the succeeding stages in the process (packaging and layout) do not care what your
schematic looks like. They only care about what’s in the netlist. So, to be absolutely
honest, in the suite I’ve been using for something over 20 years, once I’ve created my
schematic and am happy with all the connections, I can pick up the 144pin TQFP CPU
in the middle of it and drag it over into a vacant corner of the sheet, rubberbanding all
144 lines with it, over top of all kinds of other stuff, turning it into a completely
unreadable mess. It’ll throw hundreds of warnings, and if I ignore those warnings and
push through to layout my PCB connections will all be exactly as they were before I
made the schematic look like an explosion at a spaghetti factory.
Let me absolutely clear: My intention isn’t to “tell [anyone] off” - I’ve been doing this for
quite a long time, so I engage in hopefully-constructive, but no less aggressive,
argument. And I’m wrong all the time, but not today, and not about this. And I
wouldn’t waste the keystrokes if not in hope that this criticism will be taken seriously and
lead to improvement.
Regarding the netlist’s relationship to the design, it’s not just a one-way thing. Because
I’m stuck at the moment in a dysfunctional schematic capture, I haven’t yet earned any
experience with KiCAD’s layout, so I don’t know what its capabilities are. Specifically,
does it support gate-swapping or package-swapping? That is, you take your best stab,
of course, at wiring the schematic in a manner that you think will make sense in layout,
but when you actually get to layout, sooner or later you’re going to realize that the
routing will benefit from swapping this gate with another in the same package, or with
another of the same type of gate in another package somewhere else on the board.
If your layout software supports it, you can do that with a click or two. But then your
layout is out of sync with the schematic it came from, so you back-annotate to carry
those swaps back into the schematic so it now correctly reflects the change on the
board. That’s a simple SSI example; a more modern one is an FPGA with a couple
of hundred pins. In layout you’re going to swap those pins around a lot, and you need
to propagate the changes back not only to the schematic but to your VHDL source as
well. So in a system that works, you normally don’t have to make the netlist your
business, because it’s taken care of.
And although I get your point, no, you wouldn’t write the netlist directly because the
schematic capture is a human-friendly tool that will translate your easy-to-understand
visual representation of the circuit into the decidedly human-unfriendly netlist database.
Think of it as a high-level language for generating a netlist. And pursuing that analogy,
there’s no point in having a C compiler that doesn’t actually generate good machine
language. You’re arguing for, given the presence of a bad compiler, writing machine
language (and I mean machine, not assembler) by hand rather than fixing the
compiler.
i meant that in KiCad specifically, the schematic → pcb relationship is mostly one-way
there is some back-annotation of at least reference designators (maybe only in nightly)
and AIUI, pin swapping is in the works
changing a footprint gets you a similar thing to changing a symbol
but with the exception that in the PCB editor, you do have a netlist, represented by a ratsnest
(and you will get DRC errors if that doesn’t match)
a major (the?) point of a high-level language is to be able to communicate the code to other people, not that it produces equivalent machine code between styles
i think a major advantage to being more explicit in making/breaking connections (which seems to be part of the thing you’re advocating for)
is that it improves readability
(in that if you break part of it, the breakage is much less ambiguous)
There are other Ecads who try keep track automatic between signal lines and symbols. It is basically the same situation if you move or rotate 90 deg of a connected symbol. Most time, the automatic result ends up in a mess what needs to be deleted by hand and draw again. This way, I dont see anything wrong if Kicad does not try to produce a mess what needs to be deleted. If you have some improvements of your schematic in mind, therefore changing the symbol, you may not expect Kicad will do automatically what is in your mind.
There are many ideas and concepts on how to solve this. Also many users address this matter from diffrent views and only a few contributors seems interested in. The current agile dev approach does not have any instruments to discuss such problems for developing any specifications to implement in smaller steps? Its clearly not a matter for a single contributor. Also the epics seems not a good discussion of matters what span from symbol editor to schematic editor.
The kind of problem in schematics increases with the appearance of high pin count BGA components. I remember an old video from a forum member speeking on a years old Kicad conference (or Fosdem ?) It explains schematics while using symbols with increased number of pins. The end is a manual edited netlist. Unfortunately I cant find this video again.
I have absolutely no idea how much work would be involved in allowing the method you suggest to be incorporated into Kicad as an alternative to the current method.
Perhaps a politely worded “Wishlist” suggestion should be placed on Gitlab…
Help > Report Bug > then follow your nose.
In comparison to the number of contributors, there are too many wishlists and mainly too many wishlists and issues what suffer from fuzzy requirements. What Kicad needs, are more detailed concept specifications. Those specifications needs to be as detailed to allow a break down into single tasks what may be implemented by more specialized contributors. To do such specifications in advance of making code, needs to have input from user and contributor comments. Its more easy to do this in a closed source project as comparison between democracy and dictatorship. There it only needs a boss with enough money to hire programmers and they have to do what the boss pays for as long as he is able to sell his ideas at market. Also in democracy there are thousands of different minds with endless discussions what delays any decisions.
If somebody comes up with a single issue in Gitlab, its sometimes hardly possible to explain how usefull it can be for the electronic design project. Mainly if it affects other issues or more than one tool or the bug isnt a bug as the behaviour is as wanted in code design for reasons of simplicity.
I remembered that the connections are preserved by drags (G). It turns out that you can start a drag, then do the rotations and flips and the connections will be preserved. This could be handy.
No it is not.
The main use of a schematic is to have a visual representation of a circuit that humans can interpret. That it can also create a netlist is a secondary goal. If you can’t see the schematic and verify it is correct, there is also no use in creating a netlist at all. It’s just Garbage in Garbage out.
It’s the same with programming. If I write a C++ program, the goal is to write text that is human readable and understandable (so don’t use the fancy but obscure language features). A lot of time is spent on writing programs, reading it again and re writing during refactoring and maintenance. That the text is also supposed to pushed though a compiler is only a secondary or tertiary goal.
Your wish of changing schematic symbols is also a result of this. If you only cared about the netlist, then you would not change the schematic symbols but just connect stuff tho the pins.
Maybe SKiDL is a decent fit for you. SKiDL is a Python library for generating netlists in KiCad. I see it as an equivalent to VHDL for schematic design. You can for example use nested loops in Python to create a 2 dimensional LED array and generate the netlist for it. It was designed quite some years ago though and I’m not sure how much maintenance it has got.
But there is some merit to what you want.
I too would like the ability to have ratsnest lines in the schematic. My use will be mainly for reverse engineering, where you re-create a PCB (from example from Gerber files or photographs), put footprints on it (Gerber files don’t have footprints). If you could then use ratsnest lines to re-create the schematic, that would make that process a lot easier and quicker. (It would not make it more reliable, because you can just keep on tinkering with the schematic until it matches with the implied netlist locked in the PCB tracks).
In all the years I’m on this forum (Just got my 6th anniversary badge) I’ve never encountered anyone as passionate about the netlist as you.
The passion is not for netlist but for schematics what shows artists qualities. There are many users who share that passion and for that reason things like francees Elektuur symbol lib exists.
So the KiCad is for those who just don’t know this, and create their perfect symbols on the first try
I have never heard before of program that can keep right connections even you modify the symbol. Because of this I always spend some time thinking how my symbol (I use only my own symbols) should look like to be easy to use at schematic. Once defined symbol I then not modify ever to be compatible with all old schematics it was used at.
If KiCad would have the possibility you describe I would spend a little less time when defining symbol for first time, and then modify it while using for the first time (not later).
Sounds good but it is (for me) certainly not on the top of features list of PCB design software.
We are changing from Xpedition and Eagle to Kicad for several reasons and are happy with what we have with Kicad. The feature you are searching for is known as fractional symbols script at the old Xpedition Design Capture. Such symbols are in library with alternate mappings as units of one symbol plus powerbox until all units of only one pin. You may assemble them in any direction and combination when drawing the schematic without touching the library. You have to take extra care for annotating the reference designators not to make any nonsense what is called “the packer” at Xpedition.
this is correct and intentional behavior of KiCad. (wires not automatically following updated/revised pins on a changed symbol.)
it is your responsibility to update the schematic as required to represent the diagram needed to produce the circuit/show visually how the circuit is wired. Granted. this at first may sound counter-productive, however… this was decided many moons ago.
At any time I wish to use the netlist(the way you describe) is to use a plugin by the name of WireIt. that will take the wires and connect it TO pins. I have used this plugin many times to reverse engineer circuit boards from (raw)traces.
