Sometimes, there is a requirement to wire some components very near to each other, and this design intention does not get transferred to the schematic. This is more problematical with more complicated circuits, or if the schematic designer and PCB layout person are different people.
Consider this situation, where (for example) the decoupling capacitors need to be right next to the chip:
The design intention is to put capacitors CU1-1, CU1-2, CU1-3 and CU1-4 right next to the IC.
When transferring to pcbnew, the far right cap CU1-4 always has a rats nest to pin 12… but there could be hundreds of capacitors and the layout guy may not be aware of the proximity requirement and neglect to give it priority placement if it is not highlighted in some manner.
In the schematic I suggest a “proximity” pair of circles (like the “place junction” circle, but a pair instead) placed (say) at the upper end of CU1-4 and pin 12. Then maybe in the schematic it can highlight somehow that that path is important to be minimized, shown both in eeschema and pcbnew (in the ratsnest).
At the left, the design intention is also to connect CU1-1 near pin 4, but by the time pcbnew renders it, that capacitor could be placed anywhere including at the far end of the board (depending where the CU1-1 capacitor is placed), because of the connection to A1V2 power. No indication of its proximity requirement is transferred to the layout person. So again, placing a pair of “proximity requirement circles” would highlight the path to indicate both to those running eeschema and pcbnew that minimizing trace distance is important.
Perhaps a second choice would be to wire as seen in CU1-2, where obviously the design intent is to have the capacitor directly wired to pin 7. However, in pcbnew, the behaviour is exactly the same as in the previous (CU1-1) case, where the capacitor can be placed far away (just as long as CU1-1 gets attached to A1V2 “somewhere” ! Drawing this way should indicate CU1-2 should always be attached directly to pin7, but again, the proximity requirement might be overlooked by the layout person.
Note case 3, where D1V2 has been disconnected from CU1-3, and the rats nest in pcbnew always attaches CU1-3 to pin 10 (instead of skipping all around the PCB as with CU1-1 and CU1-2), but again, there is no emphasis to the layout guy that this proximity is important. In case 3, manual intervention at the layout stage to connect D1V2 is needed, but of course this may be overlooked in the complexity, leading to errors, so is the worst work-around.