I’m looking into KiCad with the possibility of moving from existing software to KiCad…
Is it possible to create “sub-assemblies” that can be reused across different projects? By “sub-assemblies” I mean complete sub-sections of a design with all components, footprints and copper layout. An example would be a DC-DC converter for which the component and copper layout is critical. Can a working design be created as a sub-assembly", placed in a library for later reuse?
You can copy schematic.sch files and reuse on other projects. I did it for a DC-DC converter as in your example. However, I guess it is not possible to reuse copper layout. There is an option to append a board, but not sure how well it will work.
Append works very well, to merge design flows.
You can append traces, and append nets or parts, or whole sub-designs.
You do need some care around nets, as append of (eg) two copies of something, will join all like-named NETs.
Append would ideally need some means to rename-local NETs on import, to separate those and merge shared NETs like GND and +5V
Part name alias can be manually managed.
If those blocks come from a master schematic, they will not have any name-conflicts, but if they have separate lineages, you need to check.
Until that rename-local feature is available, you will need to manage the rename of Nets & RefDes yourself. eg either with a script, or with a Text editor.
I can find GetReference() & SetReference() & GetNetname(), but SetNetName() is elusive ?
I find an example script, mentioned in other threads, which does rename reference by XY, but can be simplified to rename-before-save with a prefix/suffix rule
More searches find this thread with a NewNetName example - seems to be a multi-step process, but rename may have a simpler path ?
(unclear about bug status from Feb ?)
Yes, if you keep the same ‘rules’ on both sides, then merge housekeeping can work better.
Common for example, is to duplicate cells using R101, R201, R301 etc rules, which are easy to follow, and even easy to apply in KiCad PCB.
Net labels that keyed off a RefDes, could follow the same rule, so 100% manual net-name may not be needed. (** See below, local temp net-labels can be anything unique, & NET import reassigns)
I’ve not uncovered yet, a means to rename a net, but suspect there is one…
If they added a SetNetName(“NewName”) (to pair with existing SetReference(“U2n”) ) that would help.
I did some more checks around this question/rule, and KiCad NET import into PCB, is reasonably intelligent.
It needs to do more than simply import, as edits may often change net names.
If you import a name-skewed NET file, (References aligned) the import process will
NET-Rename those PADS, and NET-rename all connected segments (ie traces that at least touch a pad).
An isolated trace (trace polyline with final rats lines only to pads) is removed from the NET tree.
( & isolated polyline deleted, if option is set)
A reuse block, is unlikely to have any isolated traces.
This means you do not need to be so careful on manual NET labels - so long as the Ref names align, the existing reuse block traces will be renamed and reconnected to the new net name from SCH, on import.
Those local (temporary) NET names do need to be unique, when the reuse block is saved, so append-board avoids same-name-connects effects.
ie a Script function like SetNetName(“NewName”) would still be needed in PCB, run before each reuse-block-save-as, but a tracking NET version is not needed for SCH side.
Sorry for beeing so direct, but I’m not happy with this script solution at all. From my intuitive point of view I would expect a “circuit library” manager like the one for the footprints - just for reuseable circuit layouts, where I could select a “sub-circuit” and paste the layout into my current layout, just like a footprint.
It seems to me that the problem here is a software technical one which is not well solved yet. With software technical I mean that the strict separation of the schematics and layout comes to a big disadvantage here. Why is it not possible to link a hierarchical sheet, which concept I find really great btw, to a layout. And in the PCB editor place the hierarchical PCB layout from the corresponding hierarchical schematics?
Sorry, for beeing so emotional but this really bothers me, since a really cool openGL canvas is working but not such an important functionality to efficiently develop circuit boards…
Yes, a more formal means of reusable circuit layouts would be nice, you could always make a code submission ?
In the interim, while we wait for your solution, I remain interested in finding a script solution.
The script would be run as SaveAsReusable on a routed fragment.
It would typically offset Reference names by Rn+N*100, and could save N copies for later multi File.Append loading. SCH side tracking would be a separate issue, but I think better SCH scripting is coming.