Stunted Thermals

Here is a puzzle - Thermals that do not quite reach !
Screen shot below. (june 19 KiCad build)

Thermals are trying to work, but whilst they look to be OK on simple stacks, they seem to get confused on rounded rectangles on more complex Stacks ?
You can see them formed, but come up short of reaching the pad.
I have seen other cases where they reach the PAD, but only just, and not enough to avoid acute copper angles.

Anyone see this effect, - there is no setting I can see for Thermal length, only widths & clearances.

Not used those pads yet, looks like a bug to me.
Did you check the gerber output of that to see if it goes through and is not just a pcbnew drawing bug?

I’ve run more tests, and it is not the Pad Shape that is the trigger, but the more complex Pad Stack.
It plots as it displays.
Does not feel like a drawing bug, as it has very carefully calculated, somehow, shorter thermal spokes.

ie if I define DIFFERENT Stacks aka sizes/shapes on F.Cu from B.Cu, even though they show as NET connected…

(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers F.Cu F.Mask)
  (net 7 GND))
(pad 1 smd roundrect (at 0 0 22) (size 1.7272 1.7272) (layers B.Cu B.Mask) (roundrect_rratio 0.1)
  (net 7 GND))

first Stack thermally connects OK, second stack tries, but comes up short.
If I ask for Solid (no thermal), it also gets confused on the more complex Pad Stack, gives a round cutout for Pin1 rounded rect pad ?!.

Addit: That variable Stack also gives a false/unwanted DRC report

ErrType(25): Hole near pad
    @ (179.070 mm,104.140 mm): Pad 1 on F.Cu, Non-copper of J2
    @ (179.070 mm,104.140 mm): Pad 1 on B.Cu, Non-copper of J2

To me it is preferable to have one stack define the Drill+Top, as that is easier to edit later.

Pattern seems to be Mounted-side thermals are OK, but opposite-side thermals come up short on non-simple PAD Stacks.

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More tests
I discovered the trigger item is the Drill, and even where the thermals do overlap by plenty, DRC still reports a Not Connected PAD.
LHS is thermals nowhere near connecting, and RHS is a sub-miniature hole, with good Horiz thermal overlap, but fails connect check.

Thermals seem to be trying to be too-clever here - they head from copper to pad, and on simple Stacks, make a complete cross-over (no gaps at all).
There seems no reason to complicate that, for multiple stacks ?

Some more tuning of PAD Stacks, and the yield improves.
Attached file connects on Fill in my June 19 build, and needs a hack/workaround of very short PAD internal traces, to make DRC-Connect happy.
DRC drill near pad errors are all gone.
NET (re)import also now generates no false connect errors.
Leaves just the Thermal-Aversion bug in PcbNew (or a too-fussy connect check?) that needs fixing ?

example of a short trace patch:

Design File:
KiCad_Thermal_Bugs_Min_Edit.kicad_pcb (45.5 KB)

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Another test case, comparing arriving-trace connect, with Thermal-Connect.
This shows DRC-Trace-Connect test is not the same as DRC-Thermal-Connect-test
(ie if highlighted trace is removed, or trimmed DRC-connect fails to ‘see’ thermal-Pad overlap)
Trace can just overlap (on co-ord basis) with a Pad, to DRC- Pass, yet thermals can well-overlap and still fail ?
( note a non stunted thermal, does pass)

Why do these not use the same DRC-connect test ?

This image also shows the unwanted void around a zero size pad.
Ideally, a zero size Pad should generate no void.
A zero Size does turn off the spoke generate, so this is nearly correct - just needs the same =0 test applied to skip void-generate.