If there are two tracks or routes leaving from a component lead and if those leads are at the opposite side of the board, the connection is cut when the part is deleted.
This is how the bug can be seen
Starting from this
It’s not a feature, and it’s not a bug.
It simply is a result of deleting part of the PCB.
When you are designing the PCB you can “abuse” THT pads to also act as via’s, but if you delete a THT footprint and their pads with it then that does not work no more.
The solution is to run DRC after changes, and also always run DRC before you create gerber files for production, and fix any issues flagged by DRC.
It is you who design PCB and not KiCad (yet 
).
After you modify schematic and then ‘Update PCB from schematic’ you typically got:
You just got 2 connections to be done. I suppose there are two connection lines at your PCB both of length 0 because tracks are routed to the same place but at opposite PCB sides.
I agree with Paul and Piotr. As far as I know no EDA package can read your mind to know how you would like to reroute after changing the schematic. In your example, what KiCad should do so that the user doesn’t have to reroute manually? What is the most probable change? Replacing the THT holes with vias would be very simple, but it would be easy to do manually, too. Someone could even write a python script to find such track ends and add vias automatically.
But more common situation would be to simplify or otherwise change the layout by deleting the tracks or parts of tracks and rerouting. It would depend on the rest of the layout.
Do you have experience with several designs so that you can tell this is so common situation with common simple solution that it would be worth making a feature?
OP, I guess you were thinking that KiCad should just leave the PTH in place or that it should replace it with a via. But it actually is part of the footprint of the component you deleted. The system is doing exactly the right thing. It probably inserted in a rats nest wire that is perpendicular to the board, that’s why you couldn’t see it. But DRC would have shown you that you had an incomplete net.
Thats right, adding vias without the users knowledge may be worse, giving the user a false “PCB is OK” message.
However, I would like, if zero-length-ratsnest-lines would be visible in the layout. May be as a small arrow or a circle or something else with ratsnest-colour ?
There’s X mark in 5.99.
There are 2 small x at OP screenshoot. I suppose it is what left from ratsnest lines.
Yes, must be. They are zoomed out.
A CAD gives warning about dangling net and puts Vias in place of PTH holes.
If KiCad doesn’t do that, it should unroute those connections.
Yes, KiCad draws a ratsnest X there (marking a dangling net) and it’s also a DRC error. But no, it doesn’t put vias automatically to replace PTH holes. It was already explained why. And also it doesn’t need to unroute those connections automatically – why should it?
KiCad just does what you tell it to.
KiCad does not try to outsmart you. If it did start deleting track segments “randomly” it would drive many users mad.
I think that retiredfeline had the most useful remark. You probably did not realise that the THT pads were part of the footprint.
If you want to remove dangling track segments, all you have to do is click: Pcbnew / Edit / Cleanup Tracks and Vias
True, but REALLY small 
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