Hello! I am creating a PCB: It is for monitoring the voltage of a 6 Cell Battery (monitoring each cell individually) that works through a JST connection and voltage division. The PCB has a STM32 chip and works through CAN communication. It would be great to get a design/layout critique and maximize the chances of this working.
Voltage Monitoring PCB Layout:
Thank you!
Hi, @mac443
Welcome to the Forum!
I don’t think I will be able to provide your answers, but you will probably be better off if you provide a schematic so that we know what is what on your pcb layout.
Not a serious problem, but I would widen the tracks up close to the width of the pads, where there is ample space to do so.
How many layers does your board have? I think you would need to show all of the layers…
Moved to Projects …space space
I would swap the placement of J4 & IC3 and J5 & IC2.
The size of the resistors near J3 looks odd to me.
Seems to be two layers. So make a copper pour with 3.3V (?) on the top layer. This will remove the wiggling supply line and show you better placement of components.
Change pad connections of the bottom GND plane to thermal reliefs if you intend to hand solder these connectors.
I prefer to have not broken GND at bottom. I would avoid this one track at bottom by going with VCC under U1.
Following this idea I would go with VCC under U1 and then distribute from there through corners and through VCC pins (way from VCC supply to any VCC pad will be shorter).
My example of such approach:
I remember reading that difference between amount of copper at top and bottom should not be too big. It is probably to avoid PCB bending during reflow soldering.
Just a general tip from my experience:
Place the caps where they belong to. C1 … C7 belong to what pins? Somewhere? Anywhere?
So during layout have the schematic open and you see exactly where you intended to place the capacitor. They should be closest to the pin (in most cases) and not somewhere on a pile in the capacitor-graveyard.
Oh, and you can select a region and move it a bit to a better place. So you don’t need to make U-turns for connections (C12).
Connection of the STM to GND could be way nicer without the loop and directly where it belongs to.
Move D1 to the right, makes no sense.
That connection between LED2 and S1 looks suspicious.
Why does LED2’s connection to ground have be to the right and not just right below?
Overall, the schematic would need some cleaning up and structure.
Schematic is very hard to read and needs some structure.
As a rule of thumb positive voltage symbols should point up, and ground and negative symbols down. Try not to run wires all over the place that are connected. It makes it very difficult to follow.
I’ve circled a few things that need tidying up.
Also run a ERC on the schematic. There will be a lot of failures due to unconnected pins. You should place a unconnected symbol on these.
What is S1? I guess it’s a switch. If so, use a switch symbol in the schematic to make this more clear. I also find it suspicious that the opposite corners of such a switch are connected to GND. Using the No_Connect flags in the schematic as GMC suggested is a good idea. This helps with verifying that pins are left unconnected on purpose, instead of by mistake, and thus ERC makes more sense.
As an alternative, you can route the unused pins to some connector. This makes it easier to re-purpose the PCB for other projects. You don’t have to populate the connector.
For the rest, the most common problem is no decent GND plane, but you did this quite nicely. Routing around Y1 could be optimized a bit, but unless you have to do EMC testing for a commercial product, it’s not such a big deal.
The JST inputs/outputs normally is not good idea route directly to any pin. The cable length, is an antenna. The fingers of mounter has ESD, is a good practice place protections. TVS, series resistors, capacitors etc etc to save the MCU life
I found MC33275 datasheet and there a sentence: “The output capacitor must be mounted as close as possible to the MC33275.”
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