I’m used to creating my own footprints, and learned from assembly that the assembly/fabrication layer is very important.
Now I decided to re-install my KiCad environment and downloaded the full set of KiCad footprints, all nicely grouped by footprint / type.
The new footprints however don’t have a fab layer, or have the value on the fab layer. That last one seems strange to me. So, it seems I have to clone/recreate most of the footprints myself again and add the fab layer boxes and references.
As I’m starting all over, I wonder how others handle this issue and do their pretty footprint management:
all self created/modified footprints are put in into a single pretty library
all self created/modified footprints are put in into separate pretty libraries (for example mw-Fiducials, mw-Housings_DIP, etc. so about the same structure as KiCad does now)
I’m used to put all my footprints into a single pretty library (currently 126 footprints), as in that case I won’t have to ‘manage’ footprints and 3D shapes all the time, I can simply put them into the same folder!
That’s odd, I find that the KiCad footprints generally have the Value on the Fab layer, it’s a rule in the KLC :
10.4. Value is filled with footprint name and is placed on the fabrication layer.
Not really sure why there is no outline on the Fab layer though, there is outline in the courtyard layer, and then a partial outline on silkscreen which I don’t find very useful.
That’s odd, I find that the KiCad footprints generally have the Value on the Fab layer, it’s a rule in the KLC :
10.4. Value is filled with footprint name and is placed on the fabrication layer.
Sorry, that is actually what I meant: why is this a rule, but the most important part for fabrication, the outline including the component reference not?
Not really sure why there is no outline on the Fab layer though, there is outline in the courtyard layer, and then a partial outline on silkscreen which I don’t find very useful.
Exactly: no outline on the Fab layer. The partial outline on the silkscreen I find usefull after assembly and during manual assembly to position the component.
I started with a single lib/pretty folder but after about 50 parts in there it got tedious to work with it that way (especially as I use atomic parts where I have a symbol for each device I use (no generics) and the footprints are pre-linked (I use cvpcb for checking only, no assignments are made in there by me).
I started with a single lib/pretty folder but after about 50 parts in there it got tedious to work with it that way (especially as I use atomic parts where I have a symbol for each device I use (no generics) and the footprints are pre-linked (I use cvpcb for checking only, no assignments are made in there by me).
Good that you mention the atomic parts thingy. I previously had problems mixing generic and atomic parts in my single library approach: I got confused
So I guess I will take the route of cloning/copying the parts I need from the KiCad libraries, prefix them with my initials and manufacturer/generic, and add the required changes such as fab outline and fab reference.
Just tested this with some fake folders and files and it does give a nice overview of the symbols and footprints I have, including 3d models.
Both the topic of layer usage, and library organization, have been discussed in other threads over the last several months. There’s a general consensus that anybody who does more than a handful of boards ends up with a collection of custom footprints and symbols, and eventually tries to organize them into a personal library. Creating an organization scheme that is efficient across many projects, and over an extended period of time, is an extremely challenging task.
Once you move beyond the essential layers there is no general agreement about exactly how they should be used. You and I even use the term “fab layer” very differently. My version of a “fab layer” tells the PCB etch and drill house how to fabricate the bare board - things like the type of laminate, its thickness, temperature rating, the layer stack-up details, leaded versus non-leaded solder plating, etc.
I have started to customize footprints with detailed component sketches and identification information on the ECO1 layer (which I refer to as the “Assembly Layer”). It looks like this:
I expect it would be useful for manual assembly, as well as documenting test, troubleshooting and repair procedures.
The silkscreen layer is currently a subject for discussion within the industry. A board that is assembled by automated equipment, then buried deep inside a product with no expectation of ever being examined by human eyes, needs no silkscreen layer. A manually assembled board needs a fair amount of silkscreen information, and something like a development proof-of concept board (that will be tested, prodded, poked and altered by a horde of engineers) can’t have too much info on the silkscreen!
The “Courtyard” layer is intended as an aid to the layout guy, so he can produce a board that is manufacturable by a given suite of machinery. Since there is some variation among placement equipment with respect to the amount of clearance required around a component, the courtyard layer may require customization.
I don’t know how the “Margin” layer is intended to be used, so it’s probably available for whatever you want to do with it.
Since there are a number of different use cases, and the same information could be presented in different ways, what is ideally needed is an abstract representation of a symbol which can be used to generate data for different uses. This means moving away from simple graphic lines on a canvas. An additional benefit is that the data could be used to generate data for different CAD packages.
SnapEDA can produce part data for several packages, I guess they have an internal database format and scripts to generate output for specific packages.
It seems that some of the rules can be automatically applied, e.g. the courtyard outline is an AABB bounding box plus 0.25mm (or whatever is required).
You’re right, you can use (or not use) the Margin layer for whatever you want, but it’s intended use is as a “setback” from the board edge, like how close you can place components/traces to the board edge. I don’t think of it so much as a keepout for mechanical constraints, but how close you can get to the board edge without damaging copper when splitting a board array up.
That confirms my original guess about the use of the “Margin” layer - marking the required setback from an edge cut, where copper is not permitted. Every fab house has a requirement for such a setback - as I recall, 0.020" (0.5 mm) is fairly typical these days. Of course, a designer may impose a larger setback region for a particular board - such as when boards will be separated, AFTER assembly, by breaking them along a V-score line.
Some designers prefer to handle this constraint by drawing their board outline (usually the “Edge.Cuts” layer in KiCAD) with lines that are twice as wide as the required setback. E.g., for the 0.020" setback, they use 0.040" (1.0 mm) lines on the Edge.Cuts layer. Then, any trace, pad, or fill zone which touches the Edge.Cuts outline is in violation of the setback rule. A little clumsy, but it avoids the problem of handling two different layers as you work. Most fab houses won’t say anything about the wide lines, since nearly all of them cut the board outline to the center of the Edge.Cuts lines.
I think the setback constraint could be handled more elegantly. At the very least, I’d like to see “Board Edge Setback” added to the DRC. An entry for “Edge Clearance” or “Edge Setback” could be added under the list of the via constraint values. Or, to get REALLY exotic, add an attribute to every arc and line segment on the Edge.Cuts layer, where you specify the minimum clearance-to-copper features for that particular segment. That would permit you to not only satisfy the global setback requirements of the fab house, but also customize the setback in the vicinity of, e.g., a conductive mounting boss where you want to avoid contact.
Since the setback is essentially just a clearance constraint - like the minimum clearance required around a pad or trace - it could be useful to have KiCAD automatically calculate the setback, and display it with very thin lines near the edge cuts, just like KiCAD displays the required clearances around pads and traces when you are routing on copper layers. Having those thin guide lines automatically generated would save the trouble of drafting the “Margin” layer in the first place, as well as handling it during layout.
After experimenting for about a week and trying out the examples given by @dchisholm (use of the eco1 layer) and @nicholas (nice set of libraries on github) I’ve come to the conclusion that the current rules/sets of footprints in the Kicad repository are useless if you want to do the assembly of boards elsewhere.
The refdes on the fabrication layer is absolute a must for assembly, so should be kept at all times.
I have removed the value on the fabrication layer and moved that to the eco1 layer in exactly the same spot as the refdes on the fabrication layer: For manual assembly I don’t care about the references, but do want to know what value comes where.
So I guess I have now:
fabricated my own set of rules, just as anybody else
refdes (%R) on the fabrication layer
value (%V) on the eco1 layer
fabricated my own library naming conventions
Kicad naming for generic footprints with my own initials ie mw-Resistors.pretty
variants on that for vender specific footprints, ie mw-Resistors_Murata.pretty
Addition of a series part for my boards like mw-Boards_Series_B.pretty
fabricated my own 3dshape naming conventsions
re-using Kicad 3dshapes use Kicad naming
my own added 3dshapes use the mw- naming
the only problem I have with the latter is that my mw3DModel path does NOT work
Of course I’m not finished with my set of rules / way of work.
I’m still thinking about:
changing everything from inches to mm (I now have a mix of mm/inches). This means I would rename the current resistor/capacitor/LED etc. from imperial (0805 is what I use most) to metric (ie footprints are renamed to 2013)
use a layout grid of 0.5mm on my PCB’s
The discussion and examples given helped a lot and I think I’m able to maintain this way of designing and documenting my PCBs!
Crosspost from the meta forum regarding making my own footprints IPC-7351C compliant.
This addresses my need for everything metric and having a solid base for my footprints!
After some experiments with Chris Pavlina’s footprints (https://github.com/cpavlina/kicad-pcblib) and modifying the scripts a bit (oops. Python was new to me) to get fabrication outlines, etc. I came to the conclusion that these footprints are indeed using the older IPC naming conventions and footprint conventions and are not easy to adapt to the latest and greatest IPC7351C version.
In other words: I will definitely use the free IPC footprint generator as the basis for my Kicad footprints, just fill in the min/max dimensions, pitch, etc. and you the footprint is auto-generated for you (14 pin, 1.27 pitch SOP):
As you can see, this one uses the latest standard:
Latest naming convention with the #of pins at the start and not anymore at the end of the filename, ie: SOIC14P127_865X600X172L84X41N.kicad_mod, great!
Horizontal orientation (“B”) with pin #1 at the lower left corner as opposed to the vertical “A” orientation
New courtyard outline
New silkscreen conventions (no silkscreen under the body of the chip!!!). You see only two lines at the top and bottom of the chip.
New pin 1 convention (no dot anymore, just a short line)
And not new, but very nice: everything is metric. Goodbye to imperial!
I just add my %R to the fabrication layer, and the %V and outline to the eco1.user layer, and my IPC-7351C compliant Kicad footprint is complete!
So apart from the existing Kicad footprint libraries I now have three extra libraries (the 3-tier system):
M…Most Material Condition (Level A): IPC-7351C_Most.pretty
N…Nominal Material Condition (Level B): IPC-7351C_Nominal.pretty --> My default.
L…Least Material Condition (Level C): IPC-7351C_Least.pretty
And with those libraries in place, I have a solid basis to migrate some of my current and new designs to IPC footprints where available without having to change any of the Kicad footprint libraries. They can co-exist
