This has been discussed before and there are various solutions that attempt to subvert the inbuilt checks and balances that we use to make sure a board follows all the design rules. Here’s a summary of my generic problem
I have an op-amp that senses the voltage across a small valued resistor (in this case two 0R15 resistors with a combined resistance of 75 mOhm. For best noise results, the ground end of R9 should terminate as close as possible to GND on the PCB where R10 and R11 attach to GND. Similarly, the R11 end of R12 should connect at close as possible to the R10/11 pair. The latter is easy to achieve because the resistors R10/11 and R12 share the same unique net. BUT, if I terminate R9 to GND where the op-amp is located, then variable ground currents will result in worse noise figures.
By creating a special NET I should be able to connect the GND end of R9 to wherever I want it to go without KiCad complaining - but, KiCad knows better and although I haven’t tested it, I’m pretty sure (for example) a “ground pour” would wipe away all my work!
What’s the best solution? Is it still a kludge in 6.0? Or haven’t I found a feature I’m not even sure how to even name!
I suppose that net-tie can be used to do things as you want. But I have never used so … try yourself.
If I had to connect it I would just connect R9 at top directly to R10 or R11 pin. If I will use GND pour not only at bottom, but also at top I would protect that connection against being included in GND zone.
This looks more like something you’d do in the PCB editor. Can’t recommend using net ties as the support is currently quite bad, that’s supposed to be fixed in Kicad 7.0. The best solution is to just note the restrictions in the schematic and then when doing the layout simply placing the components appropriately. If for some reasons fills cause a problem, you can simply exclude the region from fills like with a keepout zone.
No need for a net-tie.
Keepout segments around/near the connection will prevent pours.
Works best after the final location of the component in question has been set.
Thanks for the suggestion Piotr, Jonathan, and Jos, but my op-amp is on the other side of the board (where it must stay for other reasons) so restricting a pour’s extent will be a real pain. Yes, it’s a big star I have!
If I find there still isn’t a simple clean solution suggestion by tomorrow, I’m going to go with a kludge where you create a dummy in-line part that generates a unique net for each arm of the star-GND you want. I haven’t actually tried it yet, but from all accounts it works (as it should) - but it’s still a kludge unless I can design a virtual-part that really is a short circuit that the “NET DETECTOR” (whatever it’s really called??) will decide is just a GND anyway and eliminate it!
Thanks again guys, I’ll tell you how it pans out tomorrow.
In version 6 foorprints can have multiple rule area properties.
Might be worth a try.
At risk of exaggeration…the idea of a sub-net sounds like something of a revelation. I wonder whether any EDA software recognizes such a thing? I was going to suggest net ties, but they are still a work-around.
Of course there is such a thing as sub-nets. But lets dismiss internet protocol as irrelevant here…
I guess I have never assumed that a schematic could include so much information as to (more or less) insure that the layout that is linked to it would be a good one.
But I could see that subnets and sub-subnets might be a big step towards that goal. Another parameter would be how to tell the software that a resistor belongs as close as possible to the op amp input for example. Another would be to establish ranking of all of these priorities: I would probably give power supply bypassing the highest rank.
I am far from claiming much knowledge of details available in some of the higher end pcb design software…but do any of them manage to pack enough information into the schematic to (at least come closer to) guaranteeing a good layout? And should KiCad try to do that?
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