Standard via between front and inner copper layer - wrong layer setup, or buggy indication?

Ok, so using this version:

Application: pcbnew
Version: (2017-11-13 revision d98fc85)-master, release build
    wxWidgets 3.0.2
    libcurl/7.35.0 OpenSSL/1.0.1f zlib/1.2.8 libidn/1.28 librtmp/2.3
Platform: Linux 4.4.0-116-generic x86_64, 64 bit, Little endian, wxGTK
Build Info:
    wxWidgets: 3.0.2 (wchar_t,wx containers,compatible with 2.8) GTK+ 2.24
    Boost: 1.54.0
    Curl: 7.35.0
    Compiler: GCC 4.8.4 with C++ ABI 1002

Build settings:

I open pcbnew, and first I do this layer setup - "Four layers, parts on Front only):

So, I want to place a via between front copper, and inner 2 copper layers. After this setup, I draw a track on front copper layer, then I draw a track on In2.Cu layer - then select the copper layer pairs to be F.Cu for “Top/Front Layer”, and In2.Cu for “Bottom/Back Layer”:

Then, starting from front layer, I draw a track, in the middle I hit right-click, “Place Through Via”, then start dragging and a track appears on In2.Cu - and I connect it to the existing track on In2.Cu. So far all looks good - until one notices the indication of the via properties:

As you can see - when the via is selected, the bottom statusbar shows “Layers: F.Cu/B.Cu” (while I would’ve expected “Layers: F.Cu/In2.Cu” - and whats more, if you edit the via properties, the “Start Layer” and “End Layer” properties/dropdowns are empty - and indeed, disabled.

So - is this that I’m seeing, an indication that I’ve setup the tracks wrong, and the via I’ve just placed actually still connects F.Cu and B.Cu (even if while placing, I got a violet line, indicating I’m placing a track on In2.Cu ?!) — or, is this simply a bug in Pcbnew’s indication (and the via connects F.Cu and In2.Cu, as intended?)

EDIT: And should I want to change the layers that this via connects - how would I do that, provided that the dropdowns on the properties window are disabled ?!

A via always connects all copper layers. It is the same as a through hole pad.

Buried vias can have a different set of copper layers they connect. (Talk to your manufacturer which pairings would be possible.)

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A through via goes from top to bottom. Always.
This via is available also to connect a track on In1.Cu or In2.Cu

When you selected Top and In2 layers, you selected the 2 layers the track is going to change back and forth any time you add a via. So, if you are laying a track on In2.Cu after the via placement you’ll be on the Top layer and the other way round, if you are on Top, your track will continue on In2.Cu.

I always recommend using through vias.
I would only use buried or blind vias if they are absolutely needed for electrical requierements.

In fact, blind and buried vias are not possible for any pair of layers. Ask your manufacturer.

Edit: Rene has answered while I was typing :slight_smile:


It’s a little confusing, but you have to select “Allow blind/buried vias” in Global Design Rules, otherwise you only get through vias, then you get appropriate options. With a through via you can route it on any layer.

I don’t know if the 3d viewer in your version shows all copper layers, might be a useful quick check.

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Hi all,

Thanks a ton for your answers!

Thanks again - I was actually unaware of this, I thought a “via” is a generic term for a “plated hole” connector between any two layers of a multi-layer (> 2) board; good to learn that is not the case.

Again, many thanks for this warning, otherwise I would have still thought that generally any manufacturer that advertises multi-layer board fabrication, has also the capability to implement “hole” connections between any two arbitrary layers.

However, my problem here is slightly simpler: I’m working on a double-sided board, which has some zones on the back layer. However, those zones increase my cognitive load while routing other things, so I’d like to hide them - but if I “unfill” the zones, then the ratsnest lines routed to those zones appear again, again increasing my cognitive load… But there’s no default way to hide just zones in Pcbnew, and so I’ve seen in Hiding nets in Pcbnew - Layout - Forums:

This workaround that I just developed may help you…
Create zones on unused layers with the net that you want to hide. You can hide the visibility and fill the zone and the net should disappear. Works for me so far

So, I just moved the zones to the In2 layer, and the cool thing is that even if I hide the In2 layer, the ratsnest of the through-holes routed to those zones, do not reappear, which is exactly what I wanted. So I came to the point in the design where I should place vias from front to the zones - which will ultimately be on the back layer; but are now on In2 so I can hide them.

And I thought, in the end when done, I could just edit all vias properties, and change the F.Cu-In2.Cu pairing, back to F.Cu-B.Cu (and of course, change the zones back to the bottom layer), and I’d easily get back to the intended double-sided design. That was my hope, at least :slight_smile:

Heh, I had done this in my actual project - but not in the example above; so I tried it again.

However, even if I check “Allow blind/buried vias” in Global Design Rules, when I do the exact same routine as in the OP, I get the exact same properties for the via placed by right-click/“Place Through Via” - the properties shown say “F.Cu/B.Cu”, and the layer dropdowns are disabled,

I have also tried with right-click/“Place Through Blind/Buried Via” - and that one’s properties indeed indicate “F.Cu/In2.Cu” (but the layer dropdowns are still disabled, so I cannot change them via GUI). In any case, that will cause me the extra trouble of changing the types of vias back…
Paragrahp 3.12
Do not show filled areas in zones


You should get additional menu options

unless something has changed in nightlies,

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No manufacturer has the capability to do that. As was mentioned earlier, there are limitations to what can actually be manufactured when it comes to blind/buried vias. It is easy to design a board which simply cannot be manufactured. Some manufacturers may have additional limitations and they all have their own minimum size capabilities. There are many good video tutorials on the net about how multilayer PCBs are manufactured that would not only enlighten you of these limitations but also why the manufacturing costs of a PCB increase significantly once you start using blind/buried vias.


Thanks again, all - as you can see, I’ve had only a superficial understanding of the limitation of layers, and its great to have this push along the way!

Many thanks - I’ve always seen those buttons, didn’t think of trying them :slight_smile:

I just did, and none of the three zone-related buttons hide the zone outline - but if I hide an inner copper layer, then that is gone too - while the ratsnest routed there does not reappear. So I’m still tempted to use the inner copper layer hiding technique, and then switch the inner layer content back to bottom layer once done…

Sorry, had a “syntax error” in my post - wrote “Through” instead of “Blind/Buried” - fixed in the post now… And just to confirm, yes, I do have all those options already.

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