Well we have several “open” models ready to use.
Mostly they come from PSPICE which also mostly is compatible with SPICE parameters. Some few are different and exclusive.
This is the point where my parser is able to “translate” or map those identical parameters and just comment those not handled.
The DIODE model example should put things a bit clear.
The parsers maps a PSPICE .model diode() to a plain SPICE line.
Now enters the more complex BJT parameters and MOS parameters. There are so many different parameters in .model NPN/PNP and .model NJF/PJF that mapping those is more tricky.
Now we enter the new era of MOS devices:
- SOME ARE SUBCKTs.
- but some (from LTSPICE) define a .model .MOS() entry line
using their own .model VDMOS() line.
If somebody, just like me, happens to have an LTSPICE ready circuit that contains models defined with their VDMOS parameter list…
And they have a complete library ready to use…
that just needs to be “mapped” from VDMOS model entry
to plain SPICE .model MOS() entry.
For example:
.model IRF6617 VDMOS(Rg=2 Vto=2.42 Rd=4.5m Rs=.8m Rb=3m Kp=60 lambda=.01 mtriode=3 Cgdmax=.7n Cgdmin=.15n Cgs=1.1n Cjo=.5n Is=1.5p ksubthres=.1 mfg=International_Rectifier Vds=30 Ron=8m Qg=11n)
The current VDMOS lib from LTSPICE contains about 1000
MOS models ready to use. None of them defined as SUBCKT.
Just their plain VDMOS parameter list.
My parser can translate a PSPICE .model MOS()
to SPICE .model MOS()
but not the LTSPICE VDMOS to MOS …
The most basic MOS HASH contains a rather different
parameter entry from VDMOS lines.
Example:
my %MOSHASH = (
AF => [ 'Flicker noise exponent' ,'', '1.0' ],
CBD => [ 'Zero-bias B-D junction capacitance' ,'', '0.0' ],
CBS => [ 'Zero-bias B-S junction capacitance' ,'', '0.0' ],
CGBO => [ 'Gate-bulk overlap capacitance per meter channel width' ,'', '0.0' ],
CGDO => [ 'Gate-drain overlap capacitance per meter channel width' ,'', '0.0' ],
CGSO => [ 'Gate-source overlap capacitance per meter channel width' ,'', '0.0' ],
CJ => [ 'Zero-bias bulk junction bottom cap. per sq-meter of junction area' ,'', '0.0' ],
CJSW => [ 'Zero-bias bulk junction sidewall cap. per meter of junction perimeter' ,'', '0.0' ],
DELTA => [ 'Width effect on threshold voltage (MOS2 and MOS3)' ,'', '0.0' ],
ETA => [ 'Static feedback (MOS3 only)' ,'', '0.0' ],
FC => [ 'Coefficient for forward-bias depletion capacitance formula' ,'', '0.5' ],
GAMMA => [ 'Bulk threshold parameter' ,'', '0.0' ],
IS => [ 'Bulk junction saturation current (I_{S})' ,'', '1.0e-14' ],
JS => [ 'Bulk junction saturation current (I_{S})' ,'', '1.0e-14' ],
KAPPA => [ 'Saturation field factor (MOS3 only)' ,'', '0.2' ],
KF => [ 'Flicker noise coefficient' ,'', '0.0' ],
KP => [ 'Transconductance parameter' ,'', '2.0e-5' ],
LAMBDA => [ 'Channel length modulation (MOS1 and MOS2 only) (\lambda)' ,'', '0.0' ],
LD => [ 'Lateral diffusion' ,'', '0.0' ],
LEVEL => [ 'Model index' ,'', '1' ],
MJ => [ 'Bulk junction bottom grading coeff.' ,'', '0.5' ],
MJSW => [ 'Bulk junction sidewall grading coeff.' ,'', '0.33' ],
NEFF => [ 'Total channel-charge (fixed and mobile) coefficient (MOS2 only)' ,'', '1.0' ],
NFS => [ 'Fast surface state density' ,'', '0.0' ],
NSS => [ 'Surface state density' ,'', '0.0' ],
NSUB => [ 'Substrate doping' ,'', '0.0' ],
PB => [ 'Bulk junction potential' ,'', '0.8' ],
PHI => [ 'Surface potential (U)' ,'', '0.6' ],
RD => [ 'Drain ohmic resistance' ,'', '0.0' ],
RS => [ 'Source ohmic resistance' ,'', '0.0' ],
RSH => [ 'Drain and source diffusion sheet resistance' ,'', '0.0' ],
THETA => [ 'Mobility modulation (MOS3 only)' ,'', '0.0' ],
TNOM => [ 'Parameter measurement temperature' ,'', '27' ],
TOX => [ 'Oxide thickness' ,'', '1.0e-7' ],
TPG => [ 'Type of gate material: +1 opp. to substrate, -1 same as substrate, 0 Al gate' ,'', '1.0' ],
UCRIT => [ 'Critical field for mobility degradation (MOS2 only)' ,'', '1.0e4' ],
UEXP => [ 'Critical field exponent in mobility degradation (MOS2 only)' ,'', '0.0' ],
UO => [ 'Surface mobility' ,'', '600' ],
UTRA => [ 'Transverse field coeff. (mobility) (deleted for MOS2)' ,'', '0.0' ],
VMAX => [ 'Maximum drift velocity of carriers' ,'', '0.0' ],
VTO => [ 'Zero-bias threshold voltage (V_{T0})' ,'', '0.0' ],
XJ => [ 'Metallurgical junction depth' ,'', '0.0' ],
);
To be all clear there is no attempt to TRANSLATE SUBCKT
whatsoever. Just the plain diode/BJT/FET/MOS models
adding the LTSPICE VDMOS as a last resource to have
their good list of models available.
Just download the “standard.mos” lib file from LTSPICE
to have the complete lib set.
Note as well that the thing is to “CONVERT” ready
available models to standard SPICE model.
Not changing a single line of code of current NGSPICE.
Plain out of the box.
The parser which i am trying already does that
with 90% success for DIODES and BJT and some FETs
But not MOS. And by no means the VDMOS
which are the most recent and powerful MOSFETs
Hope that sorts out the POV.
Regards
Paul
