Specific layout requirements of the Ethernet port


I finish my PCB which i use an ethernet PHY with RJ45 Connector including magnetic module. and i want to verify it,

so when i was searching in the web to see if the ethernet module was OK. i found that the layout requirements for the ethernet are strict.

here’s for example this link
page 2: http://ftp1.digi.com/support/documentation/022-0137_F.pdf

and another link : http://armbedded.eu/documentation/html/panelcardtechnicalreference/ch05s03.html

the distance trace between the PHY and ethernet is a little bit more than 1". the maximum is 3" (OK)
unfortunately i used a via to connect the Tx+/Tx- and Rx+/Rx- traces here’s a photo (in this photo only the Tx+/Tx- and Rx+/Rx- traces are active and the VIA doesn’t appears) :

as you can see i connect directly with the top copper the pull up resistance and then i put VIA to connect the wire to the RJ45 connector through the bottom side. and in the requirements they say ‘No vias or layerchanges are allowed’

so i think is better to connect directly the PHY and the RJ45 CONNECTOR with the TOP COPPER and put a VIA to connect the pull up resistor.
here’s a simplified picture of the path that i want to draw it :

i’ll manage to move on some component to create the path but the only problem that I will be forced to re-do the traces of the crystal to the bottom side and then put a VIA which is not appreciated.

here’s the schematic of the PHY/RJ45 Connector which i show the old path (bottom/top cooper) and the new one !

what do you think ?? any ADVICES ??
and how can i know the impedance of wires which sould be under the 50 Ohm as described in the requirement ?

I think i resolved the problem :

i rotate the PHY chip, so i reduced the length and no VIA at all in the (Rx+/- , Tx+/-) traces.
and the crystal i bring it close to the PHY and no VIA too.

its takes me a half day to do all this.