Spacing via/via and via/track on same net

Layout
1

PCB manufacturer had those rules:

  • 0.005” minimum trace/pad spacing
  • 0.006” minimum spacing from copper traces/pads to copper pour (copper plane)

And I got some problems with that, when via/via and via/track spacing is smaller coz of same net. But manufacturer dont care about nets.
11qaq
1qaq

For Kicad its not and error coz of same net, but for manufacturer it is.

So question:
How can I make that this dont happens again, how Kicad DRC could detect it?

2

This topic was automatically closed 90 days after the last reply. New replies are no longer allowed.