[SOLVED] Zone clearences too small

I started a new layout and I realized that the clearences for the zone are not being respected:

and I am not sure why.

The zones settings are:

and the net classes are:

they all look normal to me, I event checked the local clearences of the footprint:

but they also look normal, does anybody have an idea what could be going on ?

Application: Pcbnew
Version: (5.1.6)-1, release build
Libraries:
    wxWidgets 3.0.4
    libcurl/7.66.0 OpenSSL/1.1.1d (Schannel) zlib/1.2.11 brotli/1.0.7 libidn2/2.2.0 libpsl/0.21.0 (+libidn2/2.1.1) nghttp2/1.39.2
Platform: Windows 8 (build 9200), 64-bit edition, 64 bit, Little endian, wxMSW
Build Info:
    wxWidgets: 3.0.4 (wchar_t,wx containers,compatible with 2.8)
    Boost: 1.71.0
    OpenCASCADE Community Edition: 6.9.1
    Curl: 7.66.0
    Compiler: GCC 9.2.0 with C++ ABI 1013

Build settings:
    USE_WX_GRAPHICS_CONTEXT=OFF
    USE_WX_OVERLAY=OFF
    KICAD_SCRIPTING=ON
    KICAD_SCRIPTING_MODULES=ON
    KICAD_SCRIPTING_PYTHON3=OFF
    KICAD_SCRIPTING_WXPYTHON=ON
    KICAD_SCRIPTING_WXPYTHON_PHOENIX=OFF
    KICAD_SCRIPTING_ACTION_MENU=ON
    BUILD_GITHUB_PLUGIN=ON
    KICAD_USE_OCE=ON
    KICAD_USE_OCC=OFF
    KICAD_SPICE=ON

EDIT: It is a bug, the round corners in the mask layer and in the copper layers are calculated differently, this can cause exposed copper and in extreme cases solder bridges. It is solved in v6.

This is a known issue of version 5. Here the original bugreport on launchpad https://bugs.launchpad.net/kicad/+bug/1563744 Should be fixed in the development version so it will be fixed in version 6.

Ugh, I was trying to find the Gitlab issue but I frequently get Error 500 when trying to search the issues, the search feel also very slow :frowning:

EDIT: Maybe just a temporary issue

@Rene_Poschl’s reference to the known issue probably pointed you to an understanding, but for those of us in the peanut gallery, let me explain more clearly.

The electrical copper clearances are being observed. The issue is the calculation for the shape of the window in the soldermask.

I’m going to focus in on the +5V pad (my apologies for the annotation, I probably should have chosen a different color than red for my annotations but I don’t feel like re-doing them after the fact):
2020-07-24 11_24_27-Window

I presume that you have the +5V net in your Power netclass, which has a clearance of 0.18mm. Your zone has a clearance of 0.25mm. I didn’t measure (and not doing this in KiCad, I’d have to count pixels and convert to mm, not something I want to bother doing for this explanation), but I bet there is probably a 0.07mm gap between the yellow net clearance line and the edge of the copper fill. But, the issue linked in above messages is all about the poor calculation of the soldermask. You can see that the soldermask “window” for the pad on the horizontal and vertical edges is nearly coincident with the net clearance line, but on the curved corners deviates (relatively) significantly from the net clearance line.

In this case it probably isn’t going to cause problems. But a slight mis-alignment of the soldermask might expose the ground pour making it easier to accidentally solder bridge a short from your powers to ground, especially when hand-soldering (either assembly or rework). Though if your design needs to be ESD hardened, you may have creepage issues.

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Thanks a lot for the explanation, from the bug report and from your explanation the issue is clear now. One last bit, could you clarify this part ?

I do not need my design ESD hardened but, I am curious about the creepage for it. Thanks!

I’m not one to discuss creepage because I really only know about it and know I know barely anything else about it. You may want to do your own research with your favorite internet search tool using a search term similar to “creepage and clearance for pcb design”.