G’day,
I’m trying to separate the negative terminal of my power input from my board GND with the use of a net tie. I’m really struggling to mate the VBATT_- solid fill with the net tie, as the solid fill boundaries recede from the net tie whenever they’re re-processed (as one would expect).
Is there a simpler way to do this? I’ve played around with some files in Altium, and it seems you can quite easily create solid fill polygons, assign them to a net, and disable any automatic processing so the polygon you draw is fixed. Is this possible in KiCad?
Pic 1 below shows the net tie hard up against the edge of the VBATT_- fill; pic 2 shows what happens when I re-process the layers (pressing ‘b’ on the keyboard).